NE5900 データシートの表示（PDF） - Philips Electronics
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NE5900 Datasheet PDF : 7 Pages
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Philips Semiconductors
Call progress decoder
Product specification
NE5900
At the start of an in-band tone (envelope output goes high), a 2.3
second interval is timed out. Transitions of the envelope during this
interval are counted to determine the signal present. At 2.3
seconds, the three bits of data representing this decision are stored
in the latch and appear at the outputs. A data valid signal goes high
at this time, signaling that the data bits, Pins 10 – 12, can be read.
The output code is as follows:
Dial Tone
Ringing Signal
Busy Signal
Re-order Tone
Overflow
Pin 12
0
1
0
0
1
Pin 11
0
0
1
0
1
Pin 10
0
0
0
1
1
The overflow condition occurs in the event that too many transitions
occur during the 2.3 second interval. This can result from noise,
voice, or other line disturbances not normally present during the
post-dialing interval. Note that the end of dial tone in interpreted as
a valid ringing signal.
The clear input resets all internal registers and the output latch, and
is to be set low after the completion of dialing. The clear input
should be pulsed high for proper operation. Recommended pulse
width is between 0.2µs and 20ms. If clear is held high when
envelope is high, a false output pulse (Pin 13) can result when clear
is returned low.
For applications where dialing is done by a person rather than by a
microprocessor, an uncertainty exists about the number of digits to
be dialed (local vs long distance). In such situations it is possible to
clear the NE5900 by application of the DTMF signal or dial pulses to
the clear pin (Pin 6). When dialing is complete, the device is cleared
and ready to respond to the next call progress unit.
Enable is held at 5V to enable Pins 10, 11, 12 and 13. When enable
is brought low, data valid is also set low. Enable must remain high
while the data is also set low. Enable must remain high while the
data is being read. The test pin is for production test only and must
be kept low in all user applications.
INPUT
ANTI-ALIAS
FILTER
SC BANDPASS
FILTER
BUFFER
EXT CLOCK
IN/XTAL1
IN/XTAL2
3.58MHz
OSCILLATOR
LOWPASS
FILTER
DIGITAL
DETECTOR
5V
R1 10kΩ
VREF
R2 10kΩ
CLEAR
IN
CLOCK
DIVIDERS
DECODER
LOGIC
ANALOG
DETECTOR
0V
TRI-STATE
ENABLE
ENVELOPE
COUNT IN
PROGRESS
DATA VALID
2.3 SECOND
TIMER
DECODER
LATCHES
TRI-STATE
BUFFERS
BIT 1
BIT 2
BIT 3
SR01144
Figure 3. Detailed Block Diagram CPD
Figure 4 shows a typical application of the call progress decoder.
In this application only one external component is needed an no
microprocessor activity other than clear is required.
Figure 5 shows the recommended direct interface to the telephone
line. Bus connection is possible by utilizing tri-state, and internal
timing is accomplished with a 3.58MHz crystal.
The designer can utilize the input signal, clock, bus, or
microprocessor interface which best serves the application. Figure
6 gives a typical timing diagram for the application of Figures 4 and
5.
1986 May 8
4
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