SAA7705H データシートの表示（PDF） - Philips Electronics

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SAA7705H

Car radio Digital Signal Processor (DSP)

Philips Electronics 

Philips Semiconductors

Car radio Digital Signal Processor (DSP)

Preliminary specification

SAA7705H

Parameter setting for the IAC detectors is done by means

of 5 different coefficients. Upon reset, the nominal setting

for a good performing IAC detector is selected.

8.1.5.1 AGC set point (1 bit)

In case the sensitivity and feed-forward factor are out of

range in a certain application, the set point of the AGC

can be shifted. The set point controls the sensitivity of

the other IAC control parameters. See bit 11 of the IAC

register (Table 11).

8.1.5.2 Threshold sensitivity offset (3 bits)

With this parameter the threshold sensitivity of the

comparator in the interfering pulse detectors can be set.

It also influences the amount of unwanted triggering.

Settings are according to Table 25.

8.1.5.3 Deviation feed-forward factor (3 bits)

This parameter determines the reduction of the sensitivity

of the detector by the absolute value of the MPX signal.

This mechanism prevents the detector from unwanted

triggering at noise with modulation peaks. In Table 24 the

possible values are given.

8.1.5.4 Suppression stretch time (3 bits)

This parameter sets the duration of the pulse suppression

after the detector has stopped sending a trigger pulse.

It can be switched off by setting the value ‘000’.

The duration can be selected in steps of one period of the

304 kHz (3.3 µs) sample frequency. In Table 23 the

possible values are given.

8.1.5.5 MPX delay (2 bits)

With this parameter the delay time between

2 and 5 samples of the 304 kHz sample frequency can be

selected. The needed value depends on the used front

end of the car radio. Settings are according to Table 22.

8.1.5.6 Level-IAC threshold (4 bits)

With this parameter the sensitivity of the comparator in the

ignition interference pulse detector can be set. It also

influences the amount of unwanted triggering.

The possible values are given in Table 21. The prefix

value ‘0000’ switches off the level-IAC function.

8.1.5.7 Level-IAC feed-forward setting (2 bits)

This parameter allows for adjusting delay differences in

the signal paths from the FM antenna to the MPX mute,

namely, via the FM level-ADC and level-IAC detection and

via the FM demodulator and MPX conversion and filtering.

These differences depend on the front end used in the car

radio. With a simultaneous appearance of a peak

disturbance at the FM level input and the MPX ADC input

of the IC, a zero delay setting takes care for the level-IAC

mute pulse to coincide with the passage of the disturbance

in the MPX mute circuit. The setting for the level-IAC

feed-forward allows to advance the mute pulse by

1 sample period or to delay it by 1 or 2 sample periods of

the 304 kHz clock, with respect to the default value.

The appropriate register bits for each setting are given in

Table 20.

8.1.5.8 Level-IAC suppression stretch time (2 bits)

This parameter sets the time that the mute pulse is

stretched when the FM level input has stopped exceeding

the threshold. The duration can be selected in steps of one

period of the 304 kHz (3.3 µs) sample frequency.

In Table 19 the possible values are given.

8.1.5.9 Dynamic IAC threshold levels

If enabled by bit 15 of the LEVELIAC register, this block

will disable temporarily all IAC actions if the MPX mono

signal exceeds a threshold deviation (threshold 1) for a

given time with a given excess amount (threshold 2). This

MPX mono signal is separated from the MPX signal with a

low-pass filter with the −3 dB corner point at 15 kHz.

The possible values of this threshold are given in

Table 18.

8.1.5.10 IAC testing mode

The internal IAC trigger signal is visible on pin DSPOUT2

if bit IACTRIGGER of the IAC register is set. In this mode

the effect of the parameter settings on the IAC

performance can be verified.

8.2 Analog source selection and analog-to-digital

conversion

8.2.1 INPUT SELECTION SWITCHES

In Fig.3 the block diagram of the input is shown. The input

selection is controlled by bits in the input selector control

register and the input selection pin SELFR.

The relationship between these bits and the switches is

indicated in Table 26.

8.2.2

SIGNAL FLOW OF THE AM, ANALOG CD AND TAPE

INPUTS

The signal of the two single-ended stereo AM inputs can

be selected by the correct values of the SEL register bits

according to Table 26.

1999 Aug 16

13

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