SAA7705H データシートの表示（PDF） - Philips Electronics

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SAA7705H

Car radio Digital Signal Processor (DSP)

Philips Electronics 

Philips Semiconductors

Car radio Digital Signal Processor (DSP)

Preliminary specification

SAA7705H

handbook, full pagewidth

AGC

on-chip

off-chip

Gm

Rbias

63

OSCIN

Cx1

clock to circuit

64

OSCOUT

65

62

VDD(OSC) VSS(OSC)

Cx2

MGM126

Fig.6 Block diagram of the oscillator circuit.

Although multiples of the crystal frequency of

11.2896 MHz fall within the FM reception band, this will not

disturb the reception. The relatively low frequency crystal

is driven in a controlled way and the resonating crystal

produces harmonics of a very low amplitude in the FM

reception band.

The block diagram of the programmable PLL is shown in

Fig.7. The oscillator is used in a fundamental mode.

The 11.2896 MHz oscillator frequency is divided by 256

and the resulting signal is fed to the phase detector as a

reference signal. The base for the clock signal is a current

controlled oscillator (free running frequency

70 to 130 MHz).

After having been divided by 4, the required clock

frequency for the DSP core is available. To close the loop

this signal is further divided by 4 and by the PLL clock

division factor N. N can be programmed with the DCSCTR

register bits PLL-DIV (see Tables 7 and 15) in the range

from 93 to 181. This provides some flexibility in the choice

of the crystal frequency.

With the recommended crystal, N = 154 and the DSP

clock frequency (fDSP) equals 27.1656 MHz. N = 154 is the

default position at start-up. By setting the AD register bit

DSPTURBO (see Tables 9 and 15), the PLL output

frequency, and consequently fDSP, can be doubled.

This feature is not used in the proposed application.

The clock frequency of the PLL oscillator divided by two

(2fDSP) is also used as the clock for the DCS block.

8.4.3 THE CLOCK BLOCK

For the digital stereo decoder a clock signal is needed

which is the 512-multiple of the pilot tone frequency of the

FM multiplex signal. This is done by the Digitally Controlled

Sampling (DCS) block, which generates this

512 × 19 kHz = 9.728 MHz clock, the DCS clock, by

locking to the pilot frequency. This block is also able to

generate other frequencies. It is controlled by the

DCSCTR and DCSDIV registers (see Tables 7 and 8).

Default settings of the DCS and the PLL guarantee correct

functioning of the DCS block.

8.4.4 SYNCHRONIZATION WITH THE CORE

In case of I2S-bus input the system can run on audio

sample frequencies of fs = 32 kHz, 38 kHz, 44.1 kHz

or 48 kHz. After processing of an input sample, the Input

flag (I-flag) of the status register (see Section 8.7) of the

DSP core is set to logic 1 during 4 clock cycles on the

falling edge of the internal or external I2S-bus WS pulses.

This flag can be tested with a conditional branch

instruction in the DSP. This synchronisation starts in

parallel with the input signal due to the short period that the

I-flag is set. It is obvious that the higher fs the lower the

number of cycles available in the DSP program.

1999 Aug 16

17

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