T431616B データシートの表示（PDF） - Taiwan Memory Technology

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コンポーネント説明

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T431616B

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616B

PIN DESCRIPTION

PIN

NAME

INPUT FUNCTION

CLK

System Clock

Active on the positive going edge to sample all input.

Disables or enables device operation by masking or enabling all input

CS

Chip Select

except CLK,CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A10/AP

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10,column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.

BA

Bank Select Address

Select bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK

RAS

Row Address Strobe with RAS low.

Enables row access & precharge.

CAS

Latches column addresses on the positive going edge of the CLK

Column Address Strobe with CAS low.

Enables column access .

WE

L(U)DQM

Write Enable

Data Input/Output

Mask

Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ DQ15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS Power Supply/Ground Power and gr ound for the input buffers and the core logic.

VDDQ /VSSQ

Data Output

Power/Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

No

This pin is recommended to be left No Connection on the device.

N.C/RFU Connection/Reserved

for Future Use

Taiwan Memory Technology, Inc. reserves the right P. 4

to change products or specifications without notice.

Publication Date: JUL. 2001

Revision:A

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