T431616D データシートの表示（PDF） - Taiwan Memory Technology
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T431616D Datasheet PDF : 74 Pages
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tm TE
CH
T431616D/E
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -0~70°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
tRC
Row cycle time
(same bank)
tRCD RAS# to CAS# delay
(same bank)
tRP
Precharge to refresh/row activate command
(same bank)
tRRD Row activate to row activate delay
(different banks)
tRAS Row activate to precharge time
(same bank)
tWR Write recovery time
tCK1
CL* = 1
tCK2 Clock cycle time
CL* = 2
tCK3
CL* = 3
tCH
Clock high time
tCL
Clock low time
tAC1 Access time from CLK
CL* = 1
tAC2 (positive edge)
CL* = 2
tAC3
CL* = 3
tCCD CAS# to CAS# Delay time
tOH
Data output hold time
tLZ
Data output low impedance
tHZ
Data output high impedance
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tPDE PowerDown Exit set-up time
tREF Refresh time
* CL is CAS# Latency.
Note:
- 5/6/7/7L
Min.
48/54/63/63
Max.
15/16/16/16
15/16/16/16
10/12/14/14
35/42/42/42
100,000
2
-/20/20/20
-/7/8/8
5/6/7/7
2/2/2.5/2.5
2/2/2.5/2.5
1
1.8/2/2/2
1
2
1
2
-/8/13/13
-/6/6.5/6.5
4.5/5/5.5/5.5
3/4/5/5
64
Unit Note
9
9
ns 9
9
Cycle
10
ns 11
11
11
Cycle
10
8
ns 11
11
ms
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
6. A.C. Test Conditions
TM Technology Inc. reserves the right
P. 19
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
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