XRD98L59AIG PDF VIEW DOWNLOAD, XRD98L59AIG データシート

XRD98L59AIG データシートの表示（PDF） - Exar Corporation

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XRD98L59AIG

CCD Image Digitizers with CDS, PGA and 10-Bit A/D

Exar Corporation

XRD98L59AIG Datasheet PDF : 37 Pages

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XRD98L59

Gain[7:0]

0 0 0 0 0 0 0 0 minimum gain (6 dB) *

1 1 1 1 1 1 1 1 maximum gain (38 dB)

Table 2. Gain Register bit assignment (Address 0000)

not used

not used Offset[5:0]

0 0 0 0 0 0 Do not use (00h)

0 0 0 0 0 1 Do not use (01h)

0 0 0 0 1 0 minimum offset (02h)

1 0 0 0 0 0 default offset (20h) *

1 1 1 1 1 1 maximum offset (3Fh)

Table 3. Target Offset Register bit assignment (Address 0001) for PGA

SBLK delay[2:0]

0 0 0 min delay *

1 1 1 max delay

SPIX delay[2:0]

0 0 0 min delay *

1 1 1 max delay

Exar test

0 0 default

01, 10, 11 do not use

Table 4. Delay Register bit assignment (Address 0010)

not used RST rej

0 switch ON*

1 clocked

Exar test

0 default

1 do not use

CLAMP opt SBLK pol SPIX pol CLAMP pol CAL pol

0 Cal only 0 active low* 0 active low* 0 active low* 0 active low*

1 Clamp+Cal* 1 active high 1 active high 1 active high 1 active high

Table 5. Clock Register bit assignment (Address 0011) for SPIX or SBLK

not used

Delay test

0 test off *

1 test on

ADCIN

0 test off *

1 test on

0 convert * 0 outputs off

1 power down 1 outputs on *

Table 6. Control Register bit assignment (Address 0100)

not used

Cal Hold

0 cal active*

1 hold value

Speed Up

0 Speed Up off

1 Speed Up on*

DNS1

0 DNS off

1 DNS on*

DNS0

0 = Wide*

1 = Narrow

Man DAC

0 automatic*

1 manual

Table 7. Calibration Register bit assignment (Address 0101)

Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the registers to default

value after PD.

Rev. 2.00

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