IR3Y38 データシートの表示（PDF） - Sharp Electronics
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IR3Y38 Datasheet PDF : 21 Pages
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Serial Interface Circuit
The IR3Y38M has a serial interface to control the
gain of the AGC amplifier and the offset of the
blanking level. This interface is constituted by a shift
register for serial-parallel conversion, data registers
and D/A converters.
The data input to SDATA is fetched and shifted at
IR3Y38M
the rising edge of the SCK. While transmitting data,
the SDATA must be low when the SCK falls. When
the SDATA is high and the SCK falls, the data on
the shift register is stored at the selected data
register at the following falling edge of the SDATA.
The stored data register is selected by the data of
the D0 and D1 bits.
SDATA
SCK
Shift Register
Store
D2-D9
D0
D1 Decoder
Select
3-bit
Register
8-bit
Register
6-bit
Register
Gain
Selector
8-bit
D/A Converter
6-bit
D/A Converter
GAIN SEL
0
1
2
3
4
5
6
7
MAXIMUM GAIN (dB)
22
25
28
31.5
34.5
38
41
43.5
SCK
AGC GAIN
OFFSET
3.3 µs min.
Dummy
Cycle
Store
SDATA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA REGISTER D9
D8
D7
D6
GAIN SEL
AGC GAIN
d0
d1
d2
d3
OFFSET
d0
d1
(Don't care)
LSB
43.5
22
GAIN SEL = 7
12
GAIN SEL = 0
0
255
Value of AGC GAIN
D5
D4
D3
D2
D1
D0
d0
d1
d2
0
0
d4
d5
d6
d7
0
1
d2
d3
d4
d5
1
0
MSB
1
1
65
–75
0
63
Value of OFFSET
9
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