TB62726AFG データシートの表示（PDF） - Toshiba

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TB62726AFG

TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic

Toshiba 

TB62726ANG/AFG

Switching Characteristics (Topr = 25°C unless otherwise specifed)

Characteristics

Symbol

Conditions

Min Typ. Max Unit

Propagation delay

Output rise time

Output fall time

Maximum CLOCK rise time

Maximum CLOCK fall time

tpLH1

CLK- OUTn , LATCH = “H”,

ENABLE = “L”

⎯

150 300

tpLH2

LATCH - OUTn ,

ENABLE = “L”

⎯

140 300

tpLH3

ENABLE - OUTn ,

LATCH = “H”

⎯

140 300

tpLH

tpHL1

CLK-SERIAL OUT

CLK- OUTn , LATCH = “H”,

ENABLE = “L”

3

6

⎯

ns

⎯

170 340

tpHL2

LATCH - OUTn ,

ENABLE = “L”

⎯

170 340

tpHL3

ENABLE - OUTn ,

LATCH = “H”

⎯

170 340

tpLH

CLK-SERIAL OUT

4

7

⎯

tor

10 to 90% of voltage waveform

40

85 150 ns

tof

90 to 10% of voltage waveform

40

70 150 ns

tr

When not on PCB

tf

⎯

⎯

5

µs

(Note 5) ⎯

⎯

5

µs

Conditions: (Refer to test circuit.)

Topr = 25°C, VDD = VIH = 3.3 V and 5 V, VOUT = 0.7 V, VIL = 0 V, REXT = 490 Ω,

VL = 3.0 V, RL = 60 Ω, CL = 10.5 pF

Note 5: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve

the timing required for data transfer. Please consider the timings carefully.

Test Circuit

IDD

VIH, VIL

Function

generator

VDD

ENABLE

CLOCK

LATCH

OUT0

OUT15

RL

CL

IOL

Logic input

waveform

SERIAL-IN

SERIAL-OUT

VL

R-EXT

GND

CL

Iref

VDD = VIH = 3.3 V

VIL = 0 V

tr = tf = 10 ns

(10% to 90%)

7

2006-06-14

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