HT9580 データシートの表示（PDF） - Holtek Semiconductor

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HT9580

Character Pager Controller

Holtek Semiconductor 

Preliminary

HT9580

Configuration register

Address

0000H

Register

Name

Config.

Bit 7

HALT

Bit 6

Bit 5

CLK_SEL OSC_MOD

Bit 4

LPM

Bit 3

RTC

Bit 2

BZ_CLK

Bit 1

MDUT

Bit 0

MGEN

State on

POR

0001 0000

Oscillator configuration

There are two clock source input pins on the

chip, the main clock and the pager decoder in-

put clock. The main clock is generated by an RC

network. The system clock may be the OSC in-

put or the X1-clock depending on bit

²CLK_SEL². The pager decoder input clock co-

mes from two external pins, X1 and X2. The fre-

quency of the sub-clock will be double that of

the X1, X2 input clock. The OSC1 main clock

will be generated from an RC network that

needs an external resistor (see Application Cir-

cuit). The system clock may be X1-clock, DF or

RC clock. If no higher frequency (RC) is needed,

the external resistor between OSC1 and OSC2

can be removed. The system clock can be

switched by bit ²CLK_SEL². If ²CLK_SEL²=0

(POR State), the system clock will be X1-clock.

In other cases, with ²CLK_SEL²=1, the OSC in-

put clock will be the system clock. The clock

switching function will assist software pro-

grammers to change the mC system clock with-

in an adequate time if necessary. The

²OSC_MOD² bit selects the OSC input clock to

be either RC or DF. If ²OSC_MOD² is set to

²low² then the RC configuration is selected, oth-

erwise the DF application is selected. The pro-

grammer should note that the condition of

²CLK_SEL², ²HALT² and ²OSC_MOD² assures

that the system clock is working properly. It is

recommended that the OSC clock source is ei-

ther DF or RC. If DF and RC are necessary, it is

required to switch the system clock to X1-clock

before switching between DF and RC. Then

switch the system clock back to the OSC input

by using bit CLK_SEL if the switching action of

DF and RC is complete. Before enter HALT

mode, the system clock must select X1-clock.

The HT9580 will generate two RTC frequen-

cies, 1Hz and 2Hz respectively, determined by

bit RTC. If the bit is logic low, the 1Hz RTC fre-

quency will be selected, otherwise the 2Hz RTC

frequency will be selected. The RTC counter is

enabled/disabled by bit RTCEN and can be

masked or not masked as determined by the bit

RTCMSK of the interrupt control register

O SC1

M a in

C lo c k

F re q u e n c y

D o u b le r

SST

1 0 - b it R ip p le

X1

C o u n te r

O S C _M O D

0:R C

1:D F

O SC

C o n tro l

O SC

In p u t

H A LT

DF

S u b - c lo c k

X 1 - c lo c k

S S T C o n tro l

X 1 - c lo c k

X 1 - c lo c k

C lo c k S e le c t

S y s te m C lo c k

C LK _S E L

0 : X 1 - c lo c k

1 : O S C In p u t

C o u n te r

1 H z & T im e O u t

2 H z & T im e O u t

R T C T im e O u t

R TC

RTC block diagram

10

April 28, 2000

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