HT9580 データシートの表示（PDF） - Holtek Semiconductor

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HT9580

Character Pager Controller

Holtek Semiconductor 

Preliminary

HT9580

The WDT 7-bit counter is programmed by bits

WS0~WS2. The division ratio for the counter is

listed in the table.

WS2

WS1

WS0

Division

Ratio

0

0

0

1:1

0

0

1

1:2

0

1

0

1:4

0

1

1

1:8

1

0

0

1:16

1

0

1

1:32

1

1

0

1:64

1

1

1

1:128

The other pair ²TMR0_PR0² and ²TMR0_PR1²

are used to select the prescaler ratio for timer0.

The definition is shown in the table.

TMR0_PR1 TMR0_PR0

TMR0

Prescaler

Ratio

0

0

1/4

0

1

1/8

1

0

1/16

1

1

1/32

X 1 - c lo c k

1 /8

9 - b it P r e s c a le r

7 - b it C o u n te r

W S 0~2

8 to 1 M U X

W D T tim e - o u t

Buzzer generator registers

Address

0003H

0004H

Register

Name

BZ-L

BZ-H

Bit 7

BZL7

BZH7

Bit 6

BZL6

BZH6

Bit 5

BZL5

BZH5

Bit 4

BZL4

BZH4

Bit 3

BZL3

BZH3

Bit 2

BZL2

BZH2

Bit 1

BZL1

BZH1

Bit 0

BZL0

BZH0

State on

POR

0000 0000

0000 0000

The buzzer generator is composed of a 16-bit

PFD counter and a duty cycle control. The coun-

ter value is set by two registers, namely BZ-H

and BZ-L. The source for this generator may be

the system clock or the X1-clock. The buzzer

generator is enabled/disabled by the register

bit ²MGEN² in the configuration regis-

ter(0000H). When this bit is set high, the

buzzer generator is activated. There is another

bit in the configuration register(0000H) which

controls the buzzer output volume, bit

²MDUT². If the bit is logic high, the output of

the BZ will be modulated by the X1-clock. The

clock source of the buzzer is selected by bit

²BZ_CLK². When BZ_CLK=0, the clock source

is the system clock. On the other hand, when

BZ_CLK=1, the value of the selector will be the

X1-clock.

The truth table for enabling/disabling the

buzzer generator is shown in the table.

1

0

MGEN

Enable the

buzzer generator

Disable the

buzzer generator

12

April 28, 2000

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