TC913B データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

TC913B

Dual Auto-Zeroed Operational Amplifiers

Microchip Technology 

3.0 DETAILED DESCRIPTION

3.1 Theory of Operation

Each of the TC913’s two Op Amps actually consists of

two amplifiers. A main amplifier is always connected

from the input to the output. A separate nulling amplifier

alternately nulls its own offset and then the offset of the

amplifier. Since each amplifier is continuously being

nulled, offset voltage drift with time, temperature and

power supply variations is greatly reduced.

All nulling circuitry is internal and the nulling operation

is transparent to the user. Offset nulling voltages are

stored on two internal capacitors. An internal oscillator

and control logic, shared by the TC913’s two amplifiers,

control the nulling process.

3.2 Pin Compatibility

The TC913 pinout is compatible with OP-14, LM358,

MC1458, LT1013, TLC322, and similar dual Op Amps.

In many circuits operating from single or ±5V supplies,

the TC913 is a drop-in replacement offering DC

performance rivaling that of the best single Op Amps.

The TC913’s amplifiers include a low-impedance class

AB output buffer. Some previous CMOS chopper

amplifiers used a high-impedance output stage which

made open-loop gain dependent on load resistance.

The TC913’s open-loop gain is not dependent on load

resistance.

TC913A/TC913B

3.3 Overload Recovery

The TC913 recovers quickly from output saturation.

Typical recovery time from positive output saturation is

20 msec. Negative output saturation recovery time is

typically 5 msec.

3.4 Avoiding Latch-up

Junction-isolated CMOS circuits inherently contain a

parasitic p-n-p-n transistor circuit. Voltages exceeding

the supplies by 0.3V should not be applied to the

device pins. Larger voltages can turn the p-n-p-n

device on, causing excessive device power supply

current and power dissipation. The TC913’s power

supplies should be established at the same time or

before input signals are applied. If this is not possible,

input current should be limited to 0.1 mA to avoid

triggering the p-n-p-n structure.

© 2006 Microchip Technology Inc.

DS21482C-page 5

Share Link: