87C196LB データシートの表示（PDF） - Intel

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87C196LB

CHMOS 16-BIT MICROCONTROLLER

Intel 

AUTOMOTIVE

Name

ANGND

CLKOUT

COMP1:0

CPVER

EA#

EPA9:8

EPA3:0

®

Type

GND

O

O

O

I

I/O

Table 4. Signal Descriptions (Continued)

Description

Analog Ground

ANGND must be connected for A/D converter and port 0 operation. ANGND

and VSS should be nominally at the same potential.

Output

Output of the internal clock generator. You can select one of three

frequencies: f, f/2, or f/4. CLKOUT has a 50% duty cycle.

CLKOUT shares a package pin with P2.7 and PACT#.

Event Processor Array (EPA) Compare Pins

These signals are the outputs of the EPA compare-only channels.

COMP1:0 share package pins with the following signals: COMP0/P6.0/EPA8

and COMP1/P6.1/EPA9.

Cumulative Program Verification

During slave programming, a high signal indicates that all locations

programmed correctly, while a low signal indicates that an error occurred during

one of the programming operations.

CPVER shares a package pin with P2.6, TXJ1850, and ONCE#.

External Access

This input determines whether memory accesses to special-purpose and

program memory partitions are directed to internal or external memory. These

accesses are directed to internal memory if EA# is held high and to external

memory if EA# is held low. For an access to any other memory location, the

value of EA# is irrelevant.

EA# also controls entry into the programming modes. If EA# is at VPP voltage

(typically +12.5 V) on the rising edge of RESET#, the microcontroller enters a

programming mode.

NOTE:

Systems with EA# tied inactive have idle time between external bus

cycles. When the address/data bus is idle, you can use ports 3 and 4

for I/O. Systems with EA# tied active cannot use ports 3 and 4 as

standard I/O; when EA# is active, these ports will function only as the

address/data bus. When EA# is active, a read or write to P3_REG,

P4_REG, P3_PIN, or P4_PIN accesses the corresponding location

(1FFCH, 1FFDH, 1FFEH, or 1FFFH) in external memory.

EA# is sampled and latched only on the rising edge of RESET#. Changing the

level of EA# after reset has no effect.

Event Processor Array (EPA) Capture/Compare Channels

High-speed input/output signals for the EPA capture/compare channels.

The EPA signals share package pins with the following signals:

EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3,

EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7:6 do not connect to

package pins. They cannot be used to capture an event, but they can function

as software timers. EPA5:4 are not implemented.

8

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