87C196LB データシートの表示（PDF） - Intel

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87C196LB

CHMOS 16-BIT MICROCONTROLLER

Intel 

®

Name

EXTINT

P0.7:2

P1.3:0

P2.7:6

P2.4

P2.2:0

P3.7:0

P4.7:0

AUTOMOTIVE

Type

I

I

I/O

I/O

I/O

I/O

Table 4. Signal Descriptions (Continued)

Description

External Interrupt

In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt

pending bit. EXTINT is sampled during phase 2. The minimum high time is one

state time.

In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the

device to resume normal operation. The interrupt need not be enabled. If the

EXTINT interrupt is enabled, the CPU executes the interrupt service routine.

Otherwise, the CPU executes the instruction that immediately follows the

command that invoked the power-saving mode.

In idle mode, asserting any enabled interrupt causes the device to resume

normal operation.

EXTINT shares a package pin with P2.2 and PROG#.

Port 0

This is a high-impedance, input-only port. Port 0 pins should not be left floating.

The port 0 signals share package pins with the A/D inputs. These pins may

individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is

possible for the pins to function simultaneously as analog and digital inputs, this

is not recommended because reading port 0 while a conversion is in process

can produce unreliable conversion results.

ANGND and VREF must be connected for port 0 to function.

P0.3:2 share package pins with ACH3:2 and P0.7:4 share package pins with

ACH7:4 and PMODE.3:0.

Port 1

This is a standard bidirectional port that shares package pins with individually

selectable special-function signals.

Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK,

P1.1/EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3.

Port 2

This is a standard bidirectional port that shares package pins with individually

selectable special-function signals.

Port 2 shares package pins with the following signals: P2.0/TXD/PVER,

P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#/RXJ1850,

P2.6/TXJ1850/ONCE#/CPVER, P2.7/OSCOUT/PACT#.

Port 3

This is a memory-mapped, 8-bit, bidirectional port with programmable open-

drain or complementary output modes. The pins are shared with the

multiplexed address/data bus, which has complementary drivers..

P3.7:0 share package pins with AD7:0 and PBUS.7:0.

Port 4

This is a memory-mapped, 8-bit, bidirectional port with open-drain or

complementary output modes. The pins are shared with the multiplexed

address/data bus, which has complementary drivers.

P4.7:0 share package pins with AD15:8 and PBUS.15:8.

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