TDA10045 データシートの表示（PDF） - Philips Electronics

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TDA10045

Single Chip DVB-T Channel Receiver

Philips Electronics 

Philips Semiconductors

Single Chip DVB-T Channel Receiver

Preliminary specification

TDA10045

FEATURES

• 2K and 8K COFDM demodulator (Fully DVB-T compliant : ETS 300-744).

• All modes supported including hierarchical modes.

• Fully automatic transmission parameters detection.

• DSP based synchronization (upgradability).

• No extra-host software required.

• On chip 10-bit ADC.

• 2nd or 1st IF variable analog input.

• Only fundamental Crystal oscillator needed.

• Frequency offset estimator to speed up the scan.

• RF Tuner input power measurement

• Parallel or serial transport stream interface.

• On chip FEC decoder.

• BER measurement (before and after Viterbi decoder)

• SNR estimation

• TPS bits I2C readable (including spare ones)

• Channel frequency response output.

• Controllable dedicated I2C tuner bus (5V tolerant).

• 2 low frequency spare DAC. (∆Σ)

• Spare I/O.

• CMOS 0.2µm technology.

APPLICATIONS

• DVB-T fully compatible.

• Digital data transmission using COFDM modulations.

DESCRIPTION

The TDA10045 is a single chip channel receiver for 2K and 8K COFDM modulated signals based on the ETSI

specification (ETSI 300 744). The device interfaces directly to an IF signal, which could be either first or second

IF and integrates a 10-bit AD converter, a NCO and a PLL, simplifying external logic requirements and limiting

system costs.

The TDA10045 performs all the COFDM demodulation tasks from IF signal to the MPEG2 transport stream. An

internal DSP core manages the synchronization and the control of the demodulation process, and implements

specialy developed software for robustness against co and adjacent channel interferers, to deal with SFN echoes

situations, and to help for a very fast scan of the bandwidth.

After base band conversion and FFT demodulation, the channel frequency response is estimated based on the

scattered pilots, filtered in both time and frequency domains. This estimation is used as a correction on the

signal, carrier by carrier. A common phase error and estimator is used to deal with the tuner phase noise.

The FEC decoder is automatically synchronized thanks to the frame synchronization algorithm that uses the TPS

information included in the modulation.

This device is controlled via an I2C bus (called master). The chip provides 2 switchable I2C bus derived from the

master. A tuner I2C bus to be disconnected from the I2C master when not necessary and an Eeprom I2C bus.

The DSP software code can be fed to the chip via the master I2C bus or via the dedicated Eeprom I2C bus.

Designed in 0.2 µm CMOS technology and housed in a 100-pin MQFP package, the TDA10045 operates over

the commercial temperature range.

2000 March 15

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