TDA7491HV13TR データシートの表示（PDF） - STMicroelectronics

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TDA7491HV13TR

20 W + 20 W dual BTL class-D audio amplifier

STMicroelectronics 

Application information

TDA7491HV

7.4

7.4.1

7.4.2

Internal and external clocks

The clock of the class-D amplifier can be generated internally or can be driven by an

external source.

If two or more class-D amplifiers are used in the same system, it is recommended that all

devices operate at the same clock frequency. This can be implemented by using one

TDA7491HV as master clock, while the other devices are in slave mode (that is, externally

clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,

SYNCLK is an output in master mode and an input in slave mode.

Master mode (internal clock)

Using the internal oscillator, the output switching frequency, FSW, is controlled by the

resistor, ROSC, connected to pin ROSC:

FSW = 106 / (64 * ROSC + 440) kHz

where ROSC is in kΩ.

In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:

FSYNCLK = 2 * FSW

For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given

below in Table 8.

Slave mode (external clock)

In order to accept an external clock input the pin ROSC must be left open, that is, floating.

This forces pin SYNCLK to be internally configured as an input as given in Table 8.

The output switching frequency of the slave devices is:

FSW = FSYNCLK / 2

Table 8.

Master

Slave

How to set up SYNCLK

Mode

ROSC

ROSC < 60 kΩ

Floating (not connected)

SYNCLK

OUTPUT

INPUT

Figure 26. Master and Slave Connection

TDA7491HV

TDA7491HV

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