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TDA8767 データシートの表示(PDF) - Philips Electronics

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TDA8767 Datasheet PDF : 20 Pages
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Philips Semiconductors
12-bit high-speed Analog-to-Digital
Converter (ADC)
Preliminary specification
TDA8767
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Voltage controlled regulator input Vref (referenced to VCCA)
Vref(FS)
full scale fixed voltage
VCCA = 5 V
Vi(p-p) Vi(p-p) input voltage amplitude
differential mode
(peak-to-peak value)
single mode; Vi = 2.5 V
Iref
input current at Vref
Outputs (referenced to DGND)
3.175
V
2.0
V
2.0
V
10
µA
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)
VOL
LOW-level output voltage IOL = 2 mA
VOH
HIGH-level output voltage IOH = 0.4 mA
IO
output current in 3-state
0.5 V < VO < VCCO
Switching characteristics
0
VCCO 0.5
20
0.5
V
VCCD V
+20 µA
CLOCK FREQUENCY fclk (see Fig.3)
fclk(min)
minimum clock frequency
SH = HIGH
SH = LOW
1
1
fclk(max)
maximum clock frequency
TDA8767H/1
10
TDA8767H/2
20
TDA8767H/3
30
tCPH
clock pulse width HIGH
tCPL
clock pulse width LOW
8.5
8.5
Analog signal processing; 50% clock duty factor; Vi Vi = 2.0 V; Vref = VCCA 2 V; see Table 1
MHz
kHz
MHz
MHz
MHz
ns
ns
LINEARITY
ILE
integral non-linearity
fclk = 4 MHz; ramp input
DLE
differential non-linearity
fclk = 4 MHz; ramp input;
no missing codes
OFER
offset error
VCCA = VCCD = VCCO = 5 V; tbf
Tamb = 25 °C; Vi = Vi; output
code = 2047
GER
gain error amplitude; spread VCCA = VCCD = VCCO = 5 V; tbf
from device to device
Tamb = 25 °C; Vi Vi = 2.0 V
BANDWIDTH (fclk = 30 MHz); note 1
B
analog bandwidth
1 dB
3 dB
tSTLH
analog input settling time full scale square wave;
LOW-to-HIGH transition
note 3
tSTHL
analog input settling time full scale square wave;
HICH-to-LOW transition
note 3
HARMONICS
THD
total harmonic distortion
fclk = 30 MHz; fi = 4.43 MHz;
note 2
±3.0 ±4.0 LSB
±0.6 ±1
LSB
tbf
LSB
tbf
LSB
9
18
tbf
tbf
MHz
MHz
ns
ns
64
dB
1999 Feb 16
8

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