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TDA8358

Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier

Philips Electronics 

Philips Semiconductors

Full bridge vertical deflection output circuit

in LVDMOS with east-west amplifier

Product specification

TDA8358J

CHARACTERISTICS

VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise

specified.

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Supplies

VP

VFB

Iq(P)(av)

Iq(P)

Iq(FB)(av)

operating supply voltage

flyback supply voltage

average quiescent supply current

quiescent supply current

average quiescent flyback supply

current

note 1

during scan

no signal; no load

during scan

7.5 12

18

V

2VP 45

66

V

−

10

15

mA

−

55

75

mA

−

−

10

mA

Inputs A and B

Vi(dif)(p-p)

differential input voltage

(peak-to-peak value)

note 2

−

1000 1500 mV

VI(bias)

II(bias)

input bias voltage

input bias current

note 2

100 880 1600 mV

−

25

35

µA

Outputs A and B

Vloss(1)

voltage loss first scan part

note 3

Io = 1.1 A

−

−

4.5 V

Io = 1.6 A

−

−

6.6 V

Vloss(2)

voltage loss second scan part

note 4

Io = −1.1 A

−

−

3.3 V

Io = −1.6 A

−

−

4.8 V

Io(p-p)

output current (peak-to-peak value)

−

−

3.2 A

LE

linearity error

Io(p-p) = 3.2 A; notes 5 and 6

adjacent blocks

−

1

2

%

non adjacent blocks

−

1

3

%

Voffset

offset voltage

∆Voffset(T) offset voltage variation with

temperature

across RM; Vi(dif) = 0 V

VI(bias) = 200 mV

VI(bias) = 1 V

across RM; Vi(dif) = 0 V

−

−

±15 mV

−

−

±20 mV

−

−

40

µV/K

VO

Gv(ol)

f−3dB(h)

Gv

∆Gv(T)

DC output voltage

open-loop voltage gain

high −3 dB cut-off frequency

voltage gain

voltage gain variation with

temperature

Vi(dif) = 0 V

notes 7 and 8

open-loop

note 9

−

0.5VP −

V

−

60

−

dB

−

1

−

kHz

−

1

−

−

−

10−4 K−1

PSRR

power supply rejection ratio

note 10

80

90

−

dB

1999 Dec 22

7

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