TDA8024T/C1 データシートの表示（PDF） - NXP Semiconductors.
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TDA8024T/C1 Datasheet PDF : 33 Pages
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NXP Semiconductors
TDA8024
Standard smart card interface
R-----1-
R2
3----.-2---6---7-
1.310
–
1
0.998
=
1.491
Therefor R2 = -1---0--0-----k------ = 40.14 k and R1 = 59.86 k.
2.49
Deactivation will be effective at V2 (1 + 1.002 1.491) = 2.967 V in any case.
If the microcontroller continues to function down to 2.97 V, the slew rate on VDD should be
less than 0.20 V/ms to ensure that clock CLK is correctly delivered to the card until time
t12 (see Figure 9).
8.3 Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1⁄2 fXTAL, 1⁄4 fXTAL or 1⁄8 fXTAL. Frequency selection
is made via inputs CLKDIV1 and CLKDIV2 (see Table 4).
Table 4. Clock frequency selection[1]
CLKDIV1
CLKDIV2
0
0
0
1
1
1
1
0
fCLK
-f-X----T---A---L-
8
-f-X----T---A---L-
4
-f-X----T---A---L-
2
fXTAL
[1] The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45% of the smallest period, and that the first and last clock pulses about the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command.
The duty factor of fXTAL depends on the signal present at pin XTAL1.
In order to reach a 45% to 55% duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48% to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45% to 55% depending on the
circuit layout and on the crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed between 45% and 55% of the
clock period.
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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