TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

TFRA08C13 OCTAL T1/E1 Framer

Preliminary Data Sheet

October 2000

Table of Contents (continued)

Contents

Page

Register Maps ...................................................................................................................................................... 176

Global Registers................................................................................................................................................ 176

Framer Parameter/Control Registers (Read-Write)........................................................................................... 177

Receive Framer Signaling Registers (Read-Only) ............................................................................................ 179

Framer Unit Parameter Register Map ............................................................................................................... 180

Transmit Signaling Registers (Read/Write) ....................................................................................................... 183

Facility Data Link Parameter/Control and Status Registers (Read-Write)......................................................... 184

Absolute Maximum Ratings.................................................................................................................................. 185

Operating Conditions............................................................................................................................................ 185

Handling Precautions ........................................................................................................................................... 185

Electrical Characteristics ...................................................................................................................................... 186

Logic Interface Characteristics .......................................................................................................................... 186

Power Supply Bypassing...................................................................................................................................... 186

Outline Diagram.................................................................................................................................................... 187

352-Pin PBGA ................................................................................................................................................... 187

Ordering Information............................................................................................................................................. 188

Figures

Page

Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)............................................................................. 11

Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)................................................. 13

Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels) ................................................ 14

Figure 4. Pin Assignment ....................................................................................................................................... 15

Figure 5. Block Diagram of Framer Line Interface .................................................................................................. 29

Figure 6. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing ......................... 30

Figure 7. T1 Frame Structure ................................................................................................................................. 34

Figure 8. T1 Transparent Frame Structure ............................................................................................................. 35

Figure 9. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ......................... 37

Figure 10. SLC-96 Frame Format........................................................................................................................... 37

Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated

Signaling Multiframe Structures .......................................................................................................................... 45

Figure 12. CEPT Transparent Frame Structure ...................................................................................................... 47

Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer................................... 52

Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)..................................................... 54

Figure 15. Facility Data Link Access Timing of the Transmit and Receive

Framer Sections in the CEPT Mode.................................................................................................................... 58

Figure 16. Transmit and Receive Sa Stack Accessing Protocol ............................................................................. 60

Figure 17. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode .............................................. 63

Figure 18. Timing Specification for TFS, TLCK, and TPD in DS1 Mode ................................................................ 63

Figure 19. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ........................................... 64

Figure 20. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode ............................. 64

Figure 21. Timing Specification for RCRCMFS in CEPT Mode.............................................................................. 65

Figure 22. Timing Specification for TFS, TLCK, and TPD in CEPT Mode.............................................................. 65

Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode ................................................ 66

Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode .......................................... 66

Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8)................................................................................ 67

Figure 26. Timing for Generation of LOPLLCK (Pin F25)....................................................................................... 69

Figure 27. The T and V Reference Points for a Typical CEPT E1 Application........................................................ 72

Figure 28. Loopback and Test Transmission Modes............................................................................................... 77

4

Lucent Technologies Inc.

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