TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

TFRA08C13 OCTAL T1/E1 Framer

Preliminary Data Sheet

October 2000

Table of Contents (continued)

Tables

Page

Table 121. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) (Y6C—Y6D) ................ 146

Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E)................................................................... 146

Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F).............................................. 146

Table 124. NT1 Errored Event Enable Register (FRM_PR16) (Y70)................................................................... 147

Table 125. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18) (Y71—Y72)............ 147

Table 126. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 147

Table 127. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 148

Table 128. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (Y74) ............................................. 148

Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75) ........................................................... 149

Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76)........................................................... 149

Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77) .............................................. 149

Table 132. Primary Time-Slot Loopback Address Register (FRM_PR24) (Y78) ................................................. 150

Table 133. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 ......................................................... 150

Table 134. Secondary Time-Slot Loopback Address Register (FRM_PR25) (Y79) ............................................ 151

Table 135. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 ......................................................... 151

Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A) ..................................... 152

Table 137. Transmission of Remote Frame Alarm and CEPT Automatic

Transmission of A Bit = 1 Control Register (FRM_PR27) (Y7B) ....................................................................... 153

Table 138. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (Y7C)............................. 154

Table 139. Sa4—Sa8 Source Register (FRM_PR29) (Y7D) ............................................................................... 154

Table 140. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29 ....................................................................... 155

Table 141. Sa4—Sa8 Control Register (FRM_PR30) (Y7E) ............................................................................... 155

Table 142. Sa Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88).............................................................. 156

Table 143. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88) ...................................................... 156

Table 144. Transmit SLC-96 FDL Format ............................................................................................................ 156

Table 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS

Control Register (FRM_PR41) (Y89) ................................................................................................................ 157

Table 146. Framer Exercise Register (FRM_PR42) (Y8A) .................................................................................. 157

Table 147. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (Y8A) ............................................................................. 158

Table 148. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (Y8B)........... 159

Table 149. Signaling Mode Register (FRM_PR44) (Y8C) ................................................................................... 160

Table 150. CHI Common Control Register (FRM_PR45) (Y8D).......................................................................... 161

Table 151. CHI Common Control Register (FRM_PR46) (Y8E) .......................................................................... 162

Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F) ........................................................................... 162

Table 153. CHI Receive Control Register (FRM_PR48) (Y90) ............................................................................ 162

Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) (Y91—Y94) ......................... 163

Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) (Y95—Y98) .......................... 163

Table 156. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) (Y99—Y9C)............................ 163

Table 157. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) (Y9D—YA0) ............................ 163

Table 158. CHI Transmit Control Register (FRM_PR65) (YA1)............................................................................ 164

Table 159. CHI Receive Control Register (FRM_PR66) (YA2) ............................................................................ 164

Table 160. Auxiliary Pattern Generator Control Register (FRM_PR69) (YA5) ..................................................... 165

Table 161. Pattern Detector Control Register (FRM_PR70) (YA6) ...................................................................... 166

Table 162. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23) (YE0—YF7) ..................... 167

Table 163. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31) (YE0—YFF) .................. 167

Table 164. FDL Register Set ((A00—A0E); (A20—A2E); (B00—B0E); (B20—B2E)

(C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E))..................................................................................... 168

Table 165. FDL Configuration Control Register (FDL_PR0) (A00; A20; B00; B20; C00; C20; D00; D20) .......... 169

Table 166. FDL Control Register (FDL_PR1) (A01; A21; B01; B21; C01; C21; D01; D21)................................. 169

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