TH8062 データシートの表示（PDF） - Melexis Microelectronic Systems

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TH8062

Voltage Regulator with LIN Transceiver

Melexis Microelectronic Systems  

2.5 Timing Diagrams

TH8062

Voltage Regulator with LIN Transceiver

50%

TxD

VBUS

tdf_TXD

95%

100%

BUS

50%

RxD

0%

50%

tdf_RXD

tdr_TXD

50%

5%

tdr_RXD

Figure 2 - Timing diagram for propagation delays

tBit

tBit

TxD

VSUP

100%

tx_dom_max

tx_dom_min

tx_rec_min

tx_rec_max

tdom(max)

trec(min)

BUS

58.1%

(61.6%)

28.4%

(25.1%)

tdom(min)

74.4%

(77.8%)

42.2%

(38.9%)

trec(max)

VSS

0%

Remark:

The levels for low slope mode are shown in brackets

58.1%

(61.6%)

28.4%

(25.1%)

Figure 3 - Timing diagram for duty cycle acc. to LIN 2.0 and J2602

TH8062 – Datasheet

3901008062

Page 11 of 38

March 2006

Rev 002

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