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TJA1042 データシートの表示(PDF) - NXP Semiconductors.

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TJA1042 Datasheet PDF : 26 Pages
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NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
7.2.5 Overtemperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, Tj(sd), the output drivers will be
disabled until the virtual junction temperature falls below Tj(sd) and TXD becomes
recessive again. Including the TXD condition ensures that output driver oscillation due to
temperature drift is avoided.
7.3 SPLIT output pin and VIO supply pin
Two versions of the TJA1042 are available, only differing in the function of a single pin.
Pin 5 is either a SPLIT output pin or a VIO supply pin.
7.3.1 SPLIT pin
Using the SPLIT pin on the TJA1042T in conjunction with a split termination network (see
Figure 4 and Figure 7) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal mode, pin SPLIT delivers a DC output voltage
of 0.5VCC. In Standby mode or when VCC is off, pin SPLIT is floating. When not used, the
SPLIT pin should be left open.
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Fig 4. Stabilization circuitry and application for version with SPLIT pin
7.3.2
VIO supply pin
Pin VIO on the TTJA1042T/3 and TJA1042TK/3 should be connected to the
microcontroller supply voltage (see Figure 8). This will adjust the signal levels of
pins TXD, RXD and STB to the I/O levels of the microcontroller. Pin VIO also provides the
internal supply voltage for the low-power differential receiver of the transceiver. For
applications running in low-power mode, this allows the bus lines to be monitored for
activity even if there is no supply voltage on pin VCC.
For versions of the TJA1042 without a VIO pin, the VIO input is internally connected to VCC.
This sets the signal levels of pins TXD, RXD and STB to levels compatible with 5 V
microcontrollers.
TJA1042
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 24 November 2017
© NXP N.V. 2017. All rights reserved.
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