LH540202D-15 データシートの表示（PDF） - Sharp Electronics

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LH540202D-15

CMOS 1024 × 9 Asynchronous FIFO

Sharp Electronics 

LH540202

CMOS 1024 × 9 Asynchronous FIFO

OPERATIONAL MODES (cont’d)

Depth Cascading

Depth cascading is implemented by configuring the

required number of LH540202s in depth-cascaded mode.

In this arrangement, the FIFOs are connected in a circular

fashion, with the Expansion Out output (XO) of each

device tied to the Expansion In input (XI) of the next

device. One FIFO in the cascade must be designated as

the ‘first-load’ device, by tying its First Load input (FL/RT)

to ground. All other devices must have their FL/RT inputs

tied HIGH. In this mode, W and R signals are shared by

all devices, while logic within each LH540202 controls the

steering of data. Only one LH540202 is enabled during

any given write cycle; thus, the common Data In inputs of

all devices are tied together. Likewise, only one

LH540202 is enabled during any given read cycle; thus,

the common Data Out outputs of all devices are wire-

ORed together

In depth-cascaded mode, external logic should be

used to generate a composite Full Flag and a composite

Empty Flag, by ANDing the FF outputs of all LH540202

devices together and ANDing the EF outputs of all devices

together. Since FF and EF are assertive-LOW signals,

this ‘ANDing’ actually is implemented using an assertive-

HIGH physical OR gate. The Half-Full Flag and the

Retransmit function are not available in depth-cascaded

mode.

W

DATA IN

9

D0 - D8

FULL

RS

XO

9

9

9

LH540202

FF

EF

RS

FL Vcc

XI

XO

9

FF

RS

9

FF

LH540202

9

EF

FL Vcc

XI

XO

LH540202

9

EF

RS

FL

XI

Figure 6. FIFO Depth Cascading

(3072 × 9)

R

DATA OUT

Q0 - Q8

EMPTY

540202-19

6

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