AD9856 データシートの表示（PDF） - Analog Devices

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AD9856

CMOS 200 MHz Quadrature Digital Upconverter

Analog Devices 

AD9856

Parameter

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency

Minimum Clock Pulse Width High (tPWH)

Minimum Clock Pulse Width Low (tPWL)

Maximum Clock Rise/Fall Time

Minimum Data Setup Time (tDS)

Minimum Data Hold Time (tDH)

Maximum Data Valid Time (tDV)

Wake-Up Time2

Minimum RESET Pulse Width High (tRH)

CMOS LOGIC INPUTS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Input Capacitance

CMOS LOGIC OUTPUTS (1 mA LOAD)

Logic 1 Voltage

Logic 0 Voltage

POWER SUPPLY

+VS Current

Full Operating Conditions3

Burst Operation (25%)

Single-Tone Mode

160 MHz Clock

120 MHz Clock

Power-Down Mode

2 Assuming 1.3 kΩ and 0.01 µF loop filter components.

3 Assuming 1.3 kW and 0.01 mF loop filter components.

Temp

Test Level Min

Typ

Max

Unit

Full

IV

Full

IV

Full

IV

Full

IV

Full

IV

Full

IV

Full

IV

Full

IV

Full

IV

25°C

I

25°C

I

25°C

I

25°C

I

25°C

V

25°C

I

25°C

I

30

30

25

0

30

5

2.6

3

2.7

10

MHz

ns

ns

1

ms

ns

ns

ns

1

ms

REFCLK cycles

V

0.4

V

12

µA

12

µA

pF

mA

0.4

mA

25°C

I

25°C

I

25°C

I

25°C

I

25°C

I

25°C

I

530

mA

450

mA

495

mA

445

mA

345

mA

2

mA

Rev. C | Page 4 of 36

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