HT62L256 データシートの表示（PDF） - Holtek Semiconductor
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HT62L256 Datasheet PDF : 10 Pages
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Preliminary
Timing Diagrams
Read cycle 1 output enable controlled (1)
A d d re s s
OE
CS
D OUT
tR C
tA A
tA O E
tO L Z
tA C S
tC L Z
tO H
tO H Z
tC H Z
D o n 't C a r e
U nused
Read cycle 2 address controlled (1, 2, 4)
tR C
A d d re s s
D OUT
tA A
tO H
Read cycle 3 chip select controlled (1, 3, 4)
A d d re s s
D OUT
tA C S
tC L Z
tO H
D o n 't C a r e
U nused
tC H Z
D o n 't C a r e
U nused
Note:
1. WE is high for read cycle
2. Device is continuously enabled, CS=VIL
3. Address is valid prior to or coincident with the CS transition low
4. OE=VIL
5. Transition is measured at ±500mV from the steady state
Rev. 0.00
5
HT62L256
August 15, 2002
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