TMC2242CR2C1 データシートの表示（PDF） - Fairchild Semiconductor
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TMC2242CR2C1
Fairchild Semiconductor
TMC2242CR2C1 Datasheet PDF : 16 Pages
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PRODUCT SPECIFICATION
TMC2242C
Table 3a. Input Data Formats and Bit Weighting
Format
SI11
SI10
S9
Two’s Comp.
-20
2-1
2-2
Unsigned
20
2-1
2-2
...
SI1
S0
...
2-10
2-11
...
2-10
2-11
Table 3b. Output Data Formats and Bit Weighting
Format
SO15
SO14
SO13
...
Two’s Comp.
-20
2-1
2-2
...
Unsigned1
20
2-1
2-2
...
-6 dB t.c.2
-20
-20
2-1
...
-6 dB Unsgn3
0
20
2-1
...
SO5
2-10
2-10
2-9
2-9
SO4
2-11
2-11
2-10
2-10
Notes:
1. Inverted offset binary is the same as unsigned, except that all bits are complemented.
2. In -6 dB interpolation modes, the two’s complement sign bit is replicated in SI15 and SI14.
3. In -6 dB interpolation mode, the unsigned MSB is preceded by a 0 in SO15.
4. A leading minus sign denotes the two’s complement sign bit.
5. In all operating modes except “interpolate -6 dB,” dc gain is exactly unity.
Table 4. Rounded LSBs as a function of RND2-0
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO8
SO8
SO8
SO8
SO8
SO8
SO8
SO8
SO7
SO7
SO7
SO7
SO7
SO7
SO7
SO7r
SO6
SO6
SO6
SO6
SO6
SO6
SO6r
z
SO5
SO5
SO5
SO5
SO5
SO5r
z
z
SO4
SO4
SO4
SO4
SO4r
z
z
z
SO3
SO3
SO3
SO3r
z
z
z
z
SO2
SO2
SO2r
z
z
z
z
z
SO1
SO1r
z
z
z
z
z
z
SO0r
z
z
z
z
z
z
z
RND2-0
000
001
010
011
1002
101
110
111
Note:
1. The “r” indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. All output drivers at and
below the rounding bit are disabled, allowing the lower output bits to be used as control inputs.
2. If SO1 = 1, format is 8 bits, viz: SO15…SO8r z…z.
Table 5. Steady-State Output Values and Limit Triggers
Input
Unsigned 2’s Comp.
FFF
7FF
C00
400
801
001
800
000
7FF
FFF
400
C00
000
800
Interpolate -6 dB
Unsigned 2’s Comp.
7FF81
3FF81
6000
2000
4008
0008
4000
0000
3FF8
FFF8
2000
00001
E000
C0001
All Other Modes
Unsigned 2’s Comp.
FFF01
7FF01
C000
4000
8010
0010
8000
0000
7FF0
FFF0
4000
00001
C000
80001
Interpretation
Unsigned 2’s Comp.
full-scale full-scale +
3/4-scale 1/2 scale +
1 LSB +
1/2-scale
Zero
1 LSB –
1/4-scale 1/2-scale –
zero
full-scale –
Notes:
1. Full-scale values are minima and maxima permitted by on-chip limiter. Transient overshoots arising from large input signal
transitions will be clipped to these limits.
7
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