TN2425TG データシートの表示（PDF） - Supertex Inc

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TN2425TG

Low Threshold Dual N-Channel Enhancement-Mode Vertical DMOS FET

Supertex Inc 

8-Lead SOIC (Narrow Body) Package Outline (TG)

8

6.00 ± 0.20

3.90 ± 0.10

4.90 ± 0.10

Note 2

TN2425TG

1

Top View

1.75 MAX

1.25 MIN

5° - 15°

(4 PLCS)

0.17 - 0.25

45°

0.25 - 0.50

Note 2

0.10 - 0.25

1.27BSC

0.31 - 0.51

Side View

0.40 - 1.27

0° - 8°

End View

Notes:

1. All dimensions in millimeters. Angles in degrees.

2. If the corner is not chamfered, then a Pin 1 identifier

must be located within the area indicated.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-TN2425TG

NR111506

5

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