W89C840AF データシートの表示（PDF） - Winbond

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W89C840AF

100/10Mbps Ethernet Controller

Winbond 

W89C840AF

Pin Descriptions

1) PCI Interface

Signal Name

PCICLK

RSTB

AD[31:0]

C_BEB[3:0]

PAR

FRAMEB

Pin

Type

I

Pin

Number

114

I

112

IO/TS

IO/TS

121-128,

5-12,

27-34,

38-45

3,15,24,

35

IO/TS

23

IO/STS

16

Pin Description

PCI Clock Input:

W89C840AF supports PCI clock rate ranged from

25Mhz to 33MHz continuously. All PCI signals except

RST# and INTA#, are referenced on the rising edge of

this clock.

PCI Hardware reset signal:

When asserted(active low), all PCI output pins of

W89C840AF will be in high impedance state, and all

open drain signals will be floated. The configurations

inside W89C840AF will be in its initial state. This

signal must be asserted for a period of at least 10 PCI

clocks to correctly take effect of a reset on hardware.

PCI Multiplexed Address and Data bus:

During the first cycle that FRAME# asserts, they act as

an address bus; on the other cycles, they are switched to

be a data bus.

Multiplexed command and byte enables:

These signals are driven by current bus master. During

address phase, they mean a bus command; on the other

phase, they present the byte enable of the transaction.

Parity signal.

This PAR represents the even parity across AD[31:0]

and C_BEB[3:0]. It has the same timing as AD[31:0]

but is delayed by one clock.

PCI Cycle Frame:

The current bus master asserts FRAMEB to indicate the

beginning and duration of a bus access. This signal

keeps asserted while the current transaction is ongoing

and keeps deasserted to indicate that the next data

phase is the final data phase.

Publication Release Date:October 2000

-6 -

Revision 1.01

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