W89C840AF データシートの表示（PDF） - Winbond

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W89C840AF

100/10Mbps Ethernet Controller

Winbond 

W89C840AF

2) BootROM and EEPROM Interface

Signal Name

Pin Type Pin

Number

BtAdd[17:0]

O

83-75,72-

64

BtAdata[7:4]

I/O

61-58

BtAdata[3]/EEDO

I/O

57

BtAdata[2]/EEDI

I/O

56

BtAdata[1]/EECK

I/O

55

BtAdata[0]

I/O

54

BtCSB

I/O

50

EECS

I/O

51

BtOEB

O

49

BtWEB

O

48

Pin Description

BootROM address bits 0 - 17

BootROM data bits 4 - 7

EEPROM data output; BootROM data bit 3

EEPROM data input; BootROM data bit 2.

EEPROM data clock; BootROM data bit 1.

BootROM data bit 0

BootROM chip select

EEPROM chip select

BootROM read enable

BootROM write enable

3) MII Interface

Signal Name

MTXCLK

MTXD[3:0]

MTXEN

MMDC

Pin

Type

I

Pin

Number

87

O

92-89

O

93

O

94

Pin Description

MII Transmit clock:

MTXCLK is a continuous uniformed clock source

driven by the external PHY. It provides the timing

reference for the signals MTXEN and MTXD.

MTXCLK should be either 25MHz or 2.5MHz clock.

MII Transmit Data:

This nibble byte width transmit data bus is synchronized

with MTXCLK. It should be latched by the external

PHY at the rising edge of MTXCLK. MTXD[0] is the

least significant bit.

MII Transmit enable:

It indicates that transmits activity to an external PHY. It

will be synchronized with MTXCLK.

MII management reference clock.

It is the reference clock of MMDIO. Each data bit will

be latched at the MMDC rising edge.

Publication Release Date:October 2000

-9 -

Revision 1.01

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