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TU25C256(1998) データシートの表示(PDF) - Turbo IC Inc

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TU25C256 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Turbo IC, Inc.
25C256
PRELIMINARY INFORMATION
Where, WPEN is the write protect enable bit. Setting WPEN to a
"1" enables the hardware write protect, and a "0"
disables the hardware write protect. This bit is
non-volatile and is programmed by the WRSR instruction.
This bit works in conjunction with the the Write
Protect (WP) pin to control the hardware write protect
feature. Hardware write protection is enabled when
the WP pin is low and the WPEN bit is "1". Hardware
write protection is disabled when either the WP pin
is high or the WPEN bit is "0". When the hardware
write protection is on, only the writes to the
the non-volatile bits (WPEN, BP1, BP0) are disabled.
It is noted that the write enable latch must also
be set before the non-volatile bits can be programmed.
Bits[6:4] are "0" except when the status register is being
programmed. These bits are read-only.
BP[1:0] are the block write protect bits. These bits
specifies which blocks in the memory array are
write protected, as indicated in Table 3. These bits
are non-volatile and are programmed by the WRSR
instruction.
WEN indicates the status of the write enable latch. A "1"
means that the write enable latch is set. A "0" means
that the write enable latch is cleared. This bit
is read-only.
BSY indicates the status of the internal write cyle to the
memory array. A "1" means that the write cycle is in
progress. A "0" means the write cycle has finished
and the device is ready for the next instruction.
This bit is read-only.
Table 3 Block "Write Protect" Assignment
---------------------------------------------------------------------------------------------
Status Register Fraction of Array Write Protected Memory Blocks
BP1 BP0 Write Protected
25C256
---------------------------------------------------------------------------------------------
0
0
0
None
---------------------------------------------------------------------------------------------
0
1
1/4
6000-
7FFF
---------------------------------------------------------------------------------------------
1
0
1/2
4000-
7FFF
---------------------------------------------------------------------------------------------
1
1
All
0000-
7FFF
---------------------------------------------------------------------------------------------
3

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