TU25C128PI-2.7 データシートの表示（PDF） - Turbo IC Inc

部品番号

コンポーネント説明

メーカー

TU25C128PI-2.7

CMOS SPI BUS 128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 16K/32K X 8 BIT EEPROM

Turbo IC Inc 

Turbo IC, Inc.

25C128/25C256

DEVICE OPERATION

The Turbo IC 25C128/25C256 has an 8-bit instruction register and an

8-bit status register. The instruction register stores one of the

operation codes defined in Table 1.

Table 1. Operation Codes

---------------------------------------------------------------------------------------------

Instruction

Operation Operation

Name

Code

Description

---------------------------------------------------------------------------------------------

WREN

00000110

Set Write Enable Latch

WRDI

00000100

Reset Write Enable Latch

RDSR

00000101

Read Status Register

WRSR

00000001

Write Status Register

READ

00000011

Read Data from Memory Array

WRITE

00000010

Write Data to Memory Array

In SPI bus convention, the master provides the serial clock

and initiates the data transfer. The Turbo IC 25C128/25C256 are

the slave devices in all applications. The master selects the

Turbo IC 25C128/25C256 by pulling CS of the device low. Once

the device is active, the master sends the operation code into

the instruction register.

The write enable latch is cleared upon power up and at the

end of the write cycle of a write instruction. Therefore, the

WREN instruction precedes all write instructions because the

write enable latch must be set before a write can be executed.

The WRDI instruction is used to clear the write enable latch

through software.

The status register gives the current operation status of the

Turbo IC 25C128/25C256. The contents of the status register is

given in Table 2.

Table 2 Status Register Contents

----------------------------------------------------------------------------------

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

----------------------------------------------------------------------------------

WPEN X

X

X BP1 BP0 WEN BSY

----------------------------------------------------------------------------------

PRELIMINARY INFORMATION

2

Share Link: