AD7869AQ データシートの表示（PDF） - Analog Devices

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AD7869AQ

LC2MOS Complete, 14-Bit Analog I/O System

Analog Devices 

AD7869

AD7869 PIN FUNCTION DESCRIPTION

DIP Pin

Number Mnemonic Function

POWER SUPPLY

7 & 23

VDD

10 & 22 VSS

8 & 19 AGND

6 & 17 DGND

Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.

Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.

Analog Ground. Both AGND pins must be tied together.

Digital Ground. Both DGND pins must be tied together.

ANALOG SIGNAL AND REFERENCE

21

VIN

ADC Analog Input. The ADC input range is ± 3 V.

9

VOUT

Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ± 3 V

with RI DAC = +3 V.

20

RO ADC

Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a

reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 µA.

11

RO DAC

DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this

internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 µA.

12

RI DAC

DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally

buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7869 is 3 V.

ADC INTERFACE AND CONTROL

2

CLK

Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS

enables the internal laser-trimmed oscillator.

3

RFS

Receive Frame Synchronization, Logic Output. This is an active low open-drain output that provides a framing

pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS.

4

RCLK

Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external

ADC clock. If the CONTROL input is at VSS, the clock runs continuously. With the CONTROL input at DGND,

the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and

requires an external 2 kΩ pull-up resistor.

5

DR

Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit

data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 kΩ resistor is

required on the DR output.

1

CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold

mode and starts an ADC conversion. This input is asynchronous to the CLK input.

24

CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-

uous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited.

DAC INTERFACE AND CONTROL

14

TFS

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial

data expected after the falling edge of this signal.

15

DT

Transmit Data, Logic Input. This is the data input that is used in conjunction with TFS and TCLK to transfer

serial data to the input latch.

16

TCLK

Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.

13

LDAC

Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge

of this signal.

18

NC

No Connect.

REV. A

DIP

CONVST 1

CLK 2

24 CONTROL

23 VDD

RFS 3

RCLK 4

DR 5

DGND 6

VDD 7

AGND 8

22 VSS

21 VIN

AD7869

TOP VIEW

(Not to Scale)

20 RO ADC

19 AGND

18 NC

17 DGND

VOUT 9

VSS 10

RO DAC 11

16 TCLK

15 DT

14 TFS

RI DAC 12

13 LDAC

NC = NO CONNECT

PIN CONFIGURATIONS

–5–

28

0.299 (7.6)

0.291 (7.39)

1

SOIC

0.708 (18.02)

0.696 (17.67)

15

0.414 (10.52)

0.398 (10.10)

14

0.096 (2.44)

0.089 (2.26)

0.03 (0.76)

0.02 (0.51) x 45°

0.01 (0.254) 0.05 0.019 (0.49)

0.006 (0.15)

(1.27)

BSC

0.014 (0.35)

6°

0.013 (0.32) 0°

0.009 (0.23)

1. LEAD NO. 1 INDENTIFIED BY A DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

0.042 (1.067)

0.018 (0.457)

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