ADG714BCPZ-REEL7(RevE) データシートの表示（PDF） - Analog Devices

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ADG714BCPZ-REEL7
(Rev.:RevE)

CMOS, Low Voltage Serially Controlled, Octal SPST Switches

Analog Devices 

ADG714/ADG715

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SCLK 1

VDD 2

DIN 3

GND 4

S1 5

D1 6

S2 7

D2 8

S3 9

D3 10

S4 11

D4 12

24 SYNC

23 RESET

22 DOUT

21 VSS

ADG714 20 S8

TOP VIEW

(Not to Scale) 19 D8

18 S7

17 D7

16 S6

15 D6

14 S5

13 D5

Figure 5. ADG714 TSSOP Pin Configuration

Table 8. ADG714 Pin Function Descriptions

Pin No.

Mnemonic Description

1

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. These devices accommodate serial input rates of up to 30 MHz.

2

VDD

Positive Analog Supply Voltage.

3

DIN

Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial

clock input.

4

GND

Ground Reference.

5, 7, 9, 11, 14, 16, 18, 20 Sx

Source. These pins may be an input or an output.

6, 8, 10, 12, 13, 15, 17, 19 Dx

Drain. These pins may be an input or an output.

21

VSS

Negative Analog Supply Voltage. For single-supply operation, tie this pin to ground.

22

DOUT

Serial Data Output. This pin allows a number of devices to be daisy-chained. Data is clocked out

of the input shift register on the rising edge of SCLK. DOUT is an open-drain output that is pulled

to the supply with an external pull-up resistor.

23

RESET

Active Low Control Input. This pin clears the input register and turns all switches to the off

condition.

24

SYNC

Active Low Control Input. This pin is the frame synchronization signal for the input data. When

SYNC goes low, this pin powers on the SCLK and DIN buffers and the input shift register is

enabled. Data is transferred on the falling edges of the following clock cycle. Taking SYNC high

updates the switches.

Rev. E | Page 10 of 21

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