ADG714BCPZ-REEL7(RevE) データシートの表示（PDF） - Analog Devices
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ADG714BCPZ-REEL7 Datasheet PDF : 21 Pages
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Data Sheet
ADG714/ADG715
Parameter
Off Switch Source Capacitance, CS (OFF)
Off Switch Drain Capacitance, CD (OFF)
On Switch Capacitance, C D (ON), C S (ON)
POWER REQUIREMENTS
Positive Power Supply Current, IDD
Negative Power Supply Current, ISS
+25°C
11
11
22
15
15
−40°C to +85°C
Unit
pF typ
pF typ
pF typ
µA typ
25
µA max
µA typ
25
µA max
Test Conditions/Comments
VDD = +2.75 V, VSS = −2.75 V
Digital inputs = 0 V or VDD
TIMING CHARACTERISTICS
ADG714
VDD = 2.7 V to 5.5 V. All specifications are from −40°C to +85°C, unless otherwise noted. See Figure 3. All input signals are specified with
tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Table 4.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t91
t10
t11
Limit at TMIN, TMAX
30
33
13
13
0
5
4.5
0
33
20
0
6
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
Conditions/Comments
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SCLK rising edge to DOUT valid
SCLK falling edge to SYNC falling edge
SYNC rising edge to SCLK rising edge
1 CL = 20 pF, RL = 1 kΩ.
ADG715
VDD = 2.7 V to 5.5 V. All specifications are from −40°C to +85°C, unless otherwise noted. See Figure 4.
Table 5.
Parameter
fSCL
t1
t2
t3
t4
t5
t61
t7
t8
t9
t10
t11
t11
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
20 + 0.1Cb2
250
300
0.1Cb2
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns max
ns min
Conditions/Comments
SCL clock frequency
SCL cycle time
SCL high time, tHIGH
SCL low time, tLOW
Start/repeated start condition hold time, tHD, STA
Data setup time, tSU, DAT
Data hold time, tHD, DAT
Setup time for repeated start, tSU, STA
Stop condition setup time, tSU, STO
Bus free time between a stop condition and a start condition, tBUF
Rise time of both SCL and SDA when receiving, tR
Fall time of SDA when receiving, tF
Fall time of SDA when transmitting, tF
Rev. E | Page 7 of 21
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