AD7226(RevA) データシートの表示（PDF） - Analog Devices

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AD7226
(Rev.:RevA)

LC2MOS Quad 8-Bit D/A Converter

Analog Devices 

AD7226–SPECIFICATIONS

DUAL SUPPLY

Parameter

(VDD = 11.4 V to 16.5 V, VSS = –5 V ؎ 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.

All specifications TMIN to TMAX unless otherwise noted.)

K, B, T Versions2

Units

Conditions/Comments

STATIC PERFORMANCE

Resolution

Total Unadjusted Error

Relative Accuracy

Differential Nonlinearity

Full Scale Error

Full Scale Temperature Coefficient

Zero Code Error

Zero Code Error Temperature Coefficient

8

±2

±1

±1

± 1 1/2

± 20

± 30

± 50

REFERENCE INPUT

Voltage Range

Input Resistance

Input Capacitance3

2 to (VDD – 4)

2

65

300

DIGITAL INPUTS

Input High Voltage, VINH

Input Low Voltage, VINL

Input Leakage Current

Input Capacitance

Input Coding

2.4

0.8

±1

8

Binary

DYNAMIC PERFORMANCE

Voltage Output Slew Rate4

2.5

Voltage Output Settling Time4

Positive Full Scale Change

5

Negative Full Scale Change

7

Digital Crosstalk

50

Minimum Load Resistance

2

POWER SUPPLIES

VDD Range

IDD

ISS

11.4/16.5

13

11

SWITCHING CHARACTERISTICS4, 5

Address to Write Setup Time, tAS

@ 25°C

0

TMIN to TMAX

0

Address to Write Hold Time, tAH

@ 25°C

10

TMIN to TMAX

10

Data Valid to Write Setup Time, tDS

@ 25°C

90

TMIN to TMAX

100

Data Valid to Write Hold Time, tDH

@ 25°C

10

TMIN to TMAX

10

Write Pulse Width, tWR

@ 25°C

150

TMIN to TMAX

200

NOTES

1Maximum possible reference voltage.

2Temperature ranges are as follows:

K Version: –40°C to +85°C

B Version: –40°C to +85°C

T Version: –55°C to +125°C

3Guanteed by design. Not production tested.

4Sample Tested at 25°C to ensure compliance.

5Switching Characteristics apply for single and dual supply operation.

Specifications subject to change without notice.

Bits

LSB max

LSB max

LSB max

LSB max

ppm/°C typ

mV max

µV/°C typ

VDD = +15 V ± 5%, VREF = +10 V

Guaranteed Monotonic

VDD = 14 V to 16.5 V, VREF = +10 V

V min to V max

kΩ min

pF min

pF max

Occurs when each DAC is loaded with all 0s.

Occurs when each DAC is loaded with all 1s.

V min

V max

µA max

pF max

VIN = 0 V or VDD

V/µs min

µs max

µs max

nV secs typ

kΩ min

V min/V max

mA max

mA max

VREF = +10 V; Settling Time to ± 1/2 LSB

VREF = +10 V; Settling Time to ± 1/2 LSB

VOUT = +10 V

For Specified Performance

Outputs Unloaded; VIN = VINL or VINH

Outputs Unloaded; VIN = VINL or VINH

ns min

ns min

ns min

ns min

ns min

ns min

ns min

ns min

ns min

ns min

–2–

REV. A

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