QL6250-5PS484C データシートの表示（PDF） - QuickLogic Corporation

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QL6250-5PS484C

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal

can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.

Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the

local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a

phase detector (the crossed circle in Figure 5) can compare the two signals. If the phases of the external and

local signals are not within the tolerance required, the phase detector sends a signal through the charge pump

and loop filter (Figure 5). The charge pump generates an error voltage to bring the VCO back into alignment

and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO

signal enters the clock tree to drive the chip's circuitry.

Fout represents the clock signal that emerges from the output pad (the output signal PLLPAD_OUT is explained

in Table 5). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it

remains in high Z state, as shown in the post-simulation waveform.

Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL presented in

Figure 5 controls the clock tree in the fourth Quadrant of its ESP. As previously mentioned, QuickLogic PLLs

compensate for the additional delay created by the clock tree itself by subtracting the clock tree delay through

the feedback path.

For more specific information on the Phase Locked Loops, refer to Application Note 58 at

http://www.quicklogic.com/images/appnote58.pdf.

PLL Modes of Operation

QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency—

Table 4 indicates the features of each mode.

PLL Model

PLL_HFb

PLL_LF

PLL_MULT2HF

PLL_MULT2LF

PLL_DIV2HF

PLL_DIV2LF

PLL_MULT4

PLL_DIV4

Table 4: PLL Mode Frequencies

Output Frequency

Input Frequency Rangea

Same as input frequency

66 MHz–150 MHz

Same as input frequency

2 × input frequency

2 × input frequency

1/2 × input frequency

1/2 × input frequency

4 × input frequency

1/4 × input frequency

25 MHz–133 MHz

50 MHz–125 MHz

16 MHz–50 MHz

100 MHz–250 MHz

50 MHz–100 MHz

16 MHz–40 MHz

100 MHz–300 MHz

Output Frequency Range

66 MHz–150 MHz

25 MHz–133 MHz

100 MHz–250 MHz

32 MHz–100 MHz

50 MHz–125 MHz

25 MHz–50 MHz

64 MHz–160 MHz

25 MHz–75 MHz

a. The input frequency can range from 12.5 MHz to 500 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you

add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies.

b. HF stands for high frequency and LF stands for low frequency.

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