TRC102 データシートの表示（PDF） - Unspecified

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TRC102

400 - 1000MHz RF Transceiver

Unspecified 

programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means

the higher the content of noise spikes in the data stream the more difficult it will be to recover clock

information as well as data.

Valid Data Detector

The DDET is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the

Clock Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The

DDET looks for valid data transitions at an expected data rate. The desired data rate and the acceptance

criteria for valid data are user programmable through the SPI port. The DDET signal is valid when using

either the internal receive FIFO or an external pin to capture baseband data. The DDET has three modes

of operation: slow, medium, fast. Each mode is dependent on what signals it uses to determine valid data

as well as the number of incoming preamble bits present at the beginning of the packet. The DDET can

be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept

only a preset range of data rates and data quality. The DDET saves battery power and time for a host

microprocessor because it will not wake up the microprocessor unless there is valid data present. See

the Receiver Control Register for a detailed description of the setup for valid data.

Receive Signal Strength Indicator (RSSI)

The TRC102 provides an analog RSSI and a digital RSSI. The digital RSSI threshold is programmable

through the Receiver Control Register and is readable through the Status Register only. When an

incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the Status Register

is set.

The analog RSSI is available through the RSSIA external pin (15). This pin requires an external capacitor

which sets the settling time. The analog RSSI may be used to recover ASK modulated data at a low rate

on the order of a few thousand bits per sec. The external capacitor value will control the received ASK

data rate allowed so choosing a lower value capacitor enables recovery of faster data at the expense of

amplitude. Using pin (15) with a sensitive comparator will yield good results.

OOK/ASK Signaling

The RSSI may be used to recover an OOK/ASK signal using an external comparator, capacitively

coupled to the RSSI output. Typically, Automatic Gain Control (AGC) is used to reduce the input signal

level upon saturation of the RSSI in the presence of strong or near-field ASK signals. The TRC102 does

not have an AGC option, however, the input LNA gain is programmable. The output RSSI signal level

may be sampled upon enabling of the receiver to test if the signal level is in saturation. If saturation is

confirmed, the input LNA gain may be reduced until the RSSI output signal level falls within the RSSI

deviation range.

Wake-Up Mode

The TRC102 has an internal wake-up timer that has very low current consumption (1.5uA typical) and

may be programmed from 1ms to several days. A calibration is performed to the crystal at startup and

every 30 sec thereafter, even if in sleep mode. If the oscillator circuit is disabled the calibration circuit will

turn it on briefly to perform a calibration to maintain accurate timing and return to sleep.

The TRC102 also incorporates other power saving modes aside from the wake-up timer. Return to active

mode may be initiated from several external events:

• Logic ‘0’ applied to nINT/DDET pin (16)

• Low Supply Voltage Detect

• FIFO Fill

• SPI request

If any of these wake-up events occur, including the wake-up timer, the TRC102 generates an external

interrupt on the nIRQ pin (5) which may be used as a wake-up signal to a host processor. The source of

the interrupt may be read out from the Status Register over the SPI bus.

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