TS8388B
Table 3. Electrical Specifications (Continued)
Parameter
Positive supply current
Analog
Digital
Negative supply voltage
Negative supply current
Analog
Digital
Nominal power dissipation
Power supply rejection ratio
Resolution
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
Analog input capacitance
Input bias current
Input Resistance
Full Power input Bandwidth (-3dB)
CBGA68 package
CQFP68 package
Small signal input Bandwidth (10% full scale)
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
ECL Clock inputs voltages (VCLK or VCLKB):
Logic “0” voltage
Logic “1” voltage
Logic “0” current
Logic “1” current
Clock input power level into 50Ω termination
Clock input power level
Clock input capacitance
Symbol
ICC
IPLUSD
VEE
AIEE
DIEE
PD
PSRR
–
VIN
VINB
VIN
VINB
CIN
IIN
RIN
FPBW
–
–
SSBW
–
–
VIL
VIH
IIL
IIH
–
–
CCLK
Test
Value
Level
Min
Typ
Max
1, 2
–
6
–
1, 2
–
6
–
385
445
395
445
115
145
120
145
1, 2, 6 -5.3
-5
-4.7
1, 2
–
6
–
1, 2
–
6
–
1, 2
–
6
–
4
–
–
–
165
200
170
200
135
180
145
180
3.4
4.1
3.6
4.3
0.5
2
8
–
4
-125
–
125
–
-125
–
125
4
-250
–
250
–
–
0
–
4
–
3
3.5
4
–
10
20
4
0.5
1
–
–
–
–
–
4
–
1.8
–
4
–
1.5
–
4
1.5
1.7
–
–
ECL or specified clock input
power level in dBm
4
–
–
–
–
–
–
-1.5
–
-1.1
–
–
–
–
5
50
–
–
5
50
–
dBm into 50Ω
4
-2
4
10
4
–
3
3.5
Unit Note
mA
mA
mA
mA
V
mA
mA
mA
mA
W
W
mW
bits
(2)
mV
mV
mV
mV
pF
µA
MΩ
–
–
GHz
GHz
GHz
–
(10)
–
V
V
µA
µA
–
dBm
pF
5
2144C–BDC–04/03