TSA5060ATS データシートの表示（PDF） - Philips Electronics

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TSA5060ATS

1.3 GHz I2C-bus controlled low phase noise frequency synthesizer

Philips Electronics 

Philips Semiconductors

1.3 GHz I2C-bus controlled low phase

noise frequency synthesizer

Product specification

TSA5060A

READ mode: R/W = 1

Data can be read out of the TSA5060A by setting bit R/W

to logic 1 (see Table 5). After the slave address has been

recognized, the TSA5060A generates an acknowledge

pulse and the first data byte (status word) is transferred on

the SDA line. Data is valid on the SDA line during a

HIGH-level of the SCL clock signal.

A second data byte can be read out of the TSA5060A if the

microcontroller generates an acknowledge bit on the

SDA line. End of transmission will occur if no acknowledge

bit from the controller occurs.The TSA5060A will then

release the data line to allow the microcontroller to

generate a STOP condition. When ports P0 to P2 are

used as inputs, they must be programmed in their

high-impedance state.

The POR flag is set to logic 1 when VCC drops below

approximately 2.75 V and at power-on.

It is reset to logic 0 when an end of data is detected by the

TSA5060A (end of a READ sequence).

Control of the loop is made possible with the in-lock flag

which indicates if the loop is phase-locked (bit FL = 1).

The bits I2, I1 and I0 represent the status of the I/O ports

P2, P1 and P0 respectively. A logic 0 indicates a

LOW-level and a logic 1 indicates a HIGH-level.

A built-in 5-level ADC is available at pin ADC. This

converter can be used to feed AFC information to the

microcontroller through the I2C-bus. The relationship

between bits A2, A1, A0 and the input voltage at pin ADC

is given in Table 7.

Table 5 Read data format

BYTE

DESCRIPTION MSB(1)

LSB

CONTROL

BIT

1 address

1

1

0

0

0 MA1 MA0 1

A

2 status byte

POR FL

I2

I1

I0

A2

A1

A0

−

Note

1. MSB is transmitted first.

Table 6 Explanation of Table 5

BIT

A

MA1 and MA0

POR

FL

I2, I1 and I0

A2, A1 and A0

DESCRIPTION

acknowledge bit

programmable address bits; see Table 3

Power-on reset flag (bit POR = 1 at power-on)

in-lock flag (bit FL = 1 when the loop is phase-locked)

digital information for I/O ports P2, P1 and P0 respectively

digital outputs of the 5-level ADC; see Table 7

Table 7 ADC levels

A2

A1

A0

1

0

0

0

1

1

0

1

0

0

0

1

0

0

0

Note

1. Accuracy is ±0.03 VCC.

0.6VCC to VCC

0.45VCC to 0.6VCC

0.3VCC to 0.45VCC

0.15VCC to 0.3VCC

0 to 0.15VCC

VOLTAGE APPLIED TO PIN ADC(1)

2000 Oct 24

8

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