5962-0324601VXC データシートの表示（PDF） - Atmel Corporation

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5962-0324601VXC

Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor

Atmel Corporation 

EDAC

Memory and I/O Parity

Memory Redundancy

Memory Access Protection

DMA

DMA Interface

Bus Arbiter

Traps

A bus time-out function of 256 system clock cycles is provided for the bus ready con-

trolled memory areas, i.e. the Extended PROM, Exchange Memory, Extended RAM,

Extended I/O and the Extended General areas.

The TSC695FL includes a 32-bit EDAC (Error Detection And Correction). Seven bits

(CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR)

is used to check and generate the odd parity over the 32-bit data bus. This means that

altogether 40 bits are used when the EDAC is enabled.

The TSC695FL EDAC uses a 7-bit Hamming code which detects any double bit error on

the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-

one and stuck-at-zero failure for any nibble in the data word as a non-correctable error.

Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-

correctable error.

The TSC695FL handles parity towards memory and I/O in a special way. The processor

can be programmed to use no parity, only parity or parity and EDAC protection towards

memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR.

Programming the Memory Configuration Register, the TSC695FL provides chip selects

for two redundant memory banks for replacement of faulty banks.

• Unimplemented Areas - Access to all unimplemented memory areas are handled by

the TSC695FL and detected as illegal.

• RAM Write Access Protection - The TSC695FL can be programmed to detect and

mask write accesses in any part of the RAM. The protection scheme is enabled only

for data area, not for the instruction area. The programmable write access

protection is based on two segments.

• Boot PROM Write Protection - The TSC695FL supports a qualified PROM write for

an 8-bit wide PROM and/or for a 40-bit wide PROM.

The TSC695FL supports Direct Memory Access (DMA). The DMA unit requests access

to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA

unit receives the DMAGNT signal in response, the processor bus is granted. In case the

processor is in the power-down mode the processor is permanent tri-stated, and a

DMAREQ will directly give a DMAGNT. The TSC695FL includes a DMA session time-

out function.

The TSC695FL always has the lowest priority on the system bus.

A trap is a vectored transfer of control to the supervisor through a special trap table that

contains the first four instructions of each trap handler. The base address of the table is

established by supervisor and the displacement, within the table, is determined by the

trap type. Two categories of traps can appear.

8 TSC695FL

4204C–AERO–05/05

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