TW9903 データシートの表示（PDF） - Unspecified

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TW9903

Multi-standard Video Decoder With High Quality Down Scaler

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TW9903

Software selectable analog inputs allow several possible input combinations:

1. Up to four composite video inputs. 2. Three composite, one S-video.

The input video signals in any certain channel maybe momentarily connected together through the

equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer cannot be

used for switching on a real-time pixel-by-pixel basis.

Clamping and Automatic Gain Control

All three analog channels have built-in clamping circuit that restore the signal DC level. The Y

channel restores the back porch of the digitized video to a level of 64 or a programmable level. The

C_Pb channel restores the back porch of the digitized video to a level of 128. This operation is

automatic through internal feedback loop.

The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a

desired level. A programmable white peak protection logic is included to prevent saturation in the

case of abnormal proportion between sync and white peak level.

Analog to Digital Converter

TW9903 contains three 8-bit pipelined ADCs that consume less power than conventional flash

ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or

the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video

signal.

Sync Processing

The sync processor of TW9903 detects horizontal synchronization and vertical synchronization

signals in the composite video or in the Y signal of an S-video or component signal. The processor

contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable

signal as well as in unstable signals such as those from VCR fast forward or backward.

Horizontal sync processing

The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL),

and the related decision logic.

The horizontal sync detector detects the presence of a horizontal sync tip by examining low-pass

filtered input samples whose level is lower than a threshold. After sufficient low levels are detected,

a horizontal sync is recognized. Additional logic is also used to avoid false detection on glitches.

The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free

image output. From there, the PLL also provides orthogonal sampling raster for the down stream

processor. The PLL has free running frequency that matches the standard raster frequency. It also

has wide lock-in range for tracking any non-standard video signal.

In case the horizontal sync is missing, a “free-wheel” mechanism keeps generating horizontal sync

signal until horizontal sync is detected again. This option can also be turned off for some

applications that determine video loss by detecting the existence of horizontal sync.

TECHWELL, INC.

6

REV. 0.92 ( B )

06/02/2002

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