TZA3005 データシートの表示（PDF） - Philips Electronics

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TZA3005

SDH/SONET STM1/OC3 and STM4/OC12 transceiver

Philips Electronics 

Philips Semiconductors

SDH/SONET STM1/OC3 and

STM4/OC12 transceiver

Objective specification

TZA3005

pattern detection is enabled and disabled by the

Out-Of-Frame (OOF) input. Detection is enabled by a

rising edge on OOF, and remains enabled while OOF is

HIGH. It is disabled when a framing pattern is detected and

OOF is no longer HIGH. When framing pattern detection is

enabled, the framing pattern is used to locate byte and

frame boundaries in the incoming data stream (Receive

Serial Data (RXSD) or looped transmitter data). The timing

generator block uses the located byte boundary to divide

the incoming data stream into bytes for output on the

parallel output data bus (RXPD0 to RXPD7). When a

48-bit pattern matching the framing pattern is detected, the

frame boundary is signalled on the Frame Pulse (FP)

output. When framing pattern detection is disabled, the

byte boundary is frozen. Only framing patterns aligned to

the fixed byte boundary are signalled on the FP output.

It is extremely unlikely that random data in an STM1/OC3

or STM4/OC12 data stream will replicate the 48-bit

framing pattern. Therefore, the time taken to detect the

beginning of the frame should be less than 250 µs (as

specified in “ITU G.783”), even for extremely high bit error

rates.

Once down-stream overhead circuitry has verified that

frame and byte synchronization are correct, the OOF input

can be set LOW to prevent the frame search process trying

to synchronize to a mimic frame pattern.

TXPD7 is the most significant bit and TXPD4 is the least

significant bit.

Parallel clock input (TXPCLK)

This is a 19.44, 38.88, 77.76 or 155.52 MHz nominally

50% duty factor TTL level input clock, to which

TXPD0 to TXPD7 are aligned. TXPCLK is used to transfer

the data on the inputs to a holding register in the

parallel-to-serial converter.

The rising edge of TXPCLK samples TXPD0 to TXPD7.

After a master reset, one rising edge of TXPCLK is

required to fully initialize the internal data path.

RECEIVER INPUT SIGNALS

Receive Serial Data (RXSD and RXSDQ)

These differential PECL serial data input signals are

normally connected to an optical receiver module or to the

TZA3004 data and clock recovery unit, and are clocked by

the RXSCLK and RXSCLKQ inputs.

Receive serial clock (RXSCLK and RXSCLKQ)

This differential PECL recovered clock signal is

synchronized to the RXSD inputs. It is used by the receive

section as the master clock for framing and deserialization

functions.

SERIAL-TO-PARALLEL CONVERTER

A delay of between 1.5 and 2.5 byte periods (or 12 to 20

serial bit periods measured from the first bit of an incoming

byte to the beginning of the parallel output of that byte)

occurs in the serial-to-parallel converter. The variation in

the delay depends on the alignment of the internal parallel

load timing, which is synchronized to the data byte

boundaries, with respect to the falling edge of RXPCLK,

which is independent of the byte boundaries. RXPCLK is

neither truncated nor extended during reframe sequences.

Transceiver pin descriptions

TRANSMITTER INPUT SIGNALS

Parallel data inputs (TXPD0 to TXPD7)

This is a 19.44, 38.88, 77.76 or 155.52 Mbytes/s TTL level

word, aligned to the TXPCLK parallel input clock. TXPD7

is the most significant bit (corresponding to bit 1 of each

PCM word, the first bit transmitted). TXPD0 is the least

significant bit (corresponding to bit 8 of each PCM word,

the last bit transmitted). TXPD0 to TXPD7 are sampled on

the rising edge of TXPCLK. If a 4-bit bus width is selected,

Out-Of-Frame (OOF)

This TTL level indicator is used to enable framing pattern

detection logic in the TZA3005. The framing pattern

detection logic is enabled by a rising edge on OOF, and

remains enabled until a frame boundary is detected or

OOF goes LOW. OOF is an asynchronous signal with a

minimum pulse width of one RXPCLK period

(see Figs 3 and 9).

Signal Detect PECL (SDPECL)

This is a PECL signal with an internal pull-down resistor.

It is active HIGH when SDTTL is at logic 0 and active LOW

when SDTTL is at logic 1. This single-ended 10K PECL

input is driven by the external optical receiver module to

indicate a loss of received optical power (Loss of Signal).

When SDPECL is inactive, the data on the serial data input

pins (RXSD and RXSDQ) will be internally forced to a

constant zero. When SDPECL is active, data on the RXSD

and RXSDQ pins will be processed normally.

When SDTTL is to be connected to the optical receiver

module instead of SDPECL, SDPECL should be tied HIGH

to implement an active LOW signal detect, or left

unconnected to implement an active HIGH signal detect.

1997 Aug 05

9

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