UDA1361TS データシートの表示（PDF） - Philips Electronics
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UDA1361TS Datasheet PDF : 20 Pages
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Philips Semiconductors
96 kHz sampling 24-bit stereo audio ADC
Product specification
UDA1361TS
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = 2.4 to 3.6 V; Tamb = −40 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
System clock timing
Tsys
system clock cycle
tCWL
tCWH
LOW-level system clock pulse
width
HIGH-level system clock pulse
width
fsys = 256fs
fsys = 384fs
fsys = 512fs
fsys = 768fs
35
88
23
59
17
44
17
30
0.40Tsys −
0.40Tsys −
780
ns
520
ns
390
ns
260
ns
0.60Tsys ns
0.60Tsys ns
Serial data timing
Tcy(CLK)(bit) bit clock period
tBCKH
tBCKL
tr
tf
td(o)(D)(BCK)
td(o)(D)(WS)
th(o)(D)
tr(WS)
tf(WS)
fWS
td(WS)(BCK)
tsu(WS)
th(WS)
bit clock HIGH time
bit clock LOW time
rise time
fall time
data output delay time
(from BCK falling edge)
data output delay time
(from WS edge)
data output hold time
word select rise time
word select fall time
word select period
word select delay from BCK
word select set-up time
word select hold time
fcy = -T--1-c---y ; master mode 64fs
64fs
64fs
Hz
fcy = -T--1-c---y ; slave mode −
−
64fs
Hz
50
−
−
ns
50
−
−
ns
−
−
20
ns
−
−
20
ns
−
−
40
ns
MSB-justified format −
−
40
ns
master mode
slave mode
slave mode
0
−
−
−
−
−
1
1
−40
−
20
−
10
−
−
ns
20
ns
20
ns
1
fs
+40
ns
−
ns
−
ns
2001 Jan 17
10
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