A67L7332E-5 データシートの表示（PDF） - AMIC Technology

部品番号

コンポーネント説明

メーカー

A67L7332E-5

256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM

AMIC Technology 

A67L8316/A67L8318/

A67L7332/A67L7336 Series

Preliminary

Features

n Fast access time: 4.0/4.2/4.5/5.0 ns

(143,133,117,100MHz)

n Direct Bus Alternation between READ and WRITE

cycles allows 100% bus utilization

n Signal +3.3V ± 5% power supply

n Individual Byte Write control capability

n Clock enable ( CEN) pin to enable clock and suspend

operations

General Description

The AMIC Direct Bus Alternation™ (DBA™ ) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

The A67L8316, A67L8318, A67L7332, A67L7336

SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or

128K X 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. These

SRAMs are optimized for 100 percent bus utilization

without the insertion of any wait cycles during Write-

Read alternation. The positive edge triggered single

clock input (CLK) controls all synchronous inputs

passing through the registers. The synchronous inputs

include all address, all data inputs, active low chip

enable ( CE ), two additional chip enables for easy depth

expansion (CE2, CE2 ), cycle start input (ADV/LD ),

synchronous clock enable ( CEN), byte write enables

(BW1,BW2 ,BW3 ,BW4 ) and read/write (R/ W ).

Asynchronous inputs include the output enable ( OE ),

clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and

burst mode (MODE). Burst Mode can provide either

interleaved or linear operation, burst operation can be

initiated by synchronous address Advance/Load

(ADV/LD ) pin in Low state. Subsequent burst address

can be internally generated by the chip and controlled by

the same input pin ADV/LD in High state.

256K X 16/18, 128K X 32/36

LVTTL, Pipelined DBA™ SRAM

n Clock-controlled and registered address, data and

control signals

n Registered output for pipelined applications

n Three separate chip enables allow wide range of

options for CE control, address pipelining

n Internally self-timed write cycle

n Selectable BURST mode (Linear or Interleaved)

n SLEEP mode (ZZ pin) provided

n Available in 100 pin LQFP package

Write cycles are internally self-time and synchronous

with the rising edge of the clock input and when R/ W is

Low. The feature simplified the write interface. Individual

Byte enables allow individual bytes to be written. BW1

controls I/Oa pins; BW2 controls I/Ob pins; BW3

controls I/Oc pins; and BW4 controls I/Od pins. Cycle

types can only be defined when an address is loaded,

i.e., when ADV/LD is LOW. Parity/ECC bits are only

available on the X18/36 version.

The SRAM operates from a +3.3V power supply, and all

inputs and outputs are LVTTL-compatible. The device is

ideally suited for high bandwidth utilization systems.

PRELIMINARY (March, 1999, Version 0.0)

1

DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc

AMIC Technology, Inc.

Share Link: