A6809SLW データシートの表示（PDF） - Allegro MicroSystems
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A6809SLW Datasheet PDF : 8 Pages
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6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
GROUND
FUNCTIONAL BLOCK DIAGRAM
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V DD
LOGIC
SUPPLY
SERIAL
DATA OUT
OUT 1 OUT 2 OUT 3
MOS
BIPOLAR
VBB
LOAD
SUPPLY
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
I1 I2 I3 ... IN-1 IN Blanklng I1 I2 I3 ... IN-1 IN
H
H R1 R2 ... RN-2 RN-1 RN-1
L
L R1 R2 ... RN-2 RN-1 RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H
P1 P2 P3 ... PN-1 PN
L
X X X ... X X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
P1 P2 P3 ... PN-1 PN
L L L ... L L
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