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UPB1008K-E1 データシートの表示(PDF) - NEC => Renesas Technology

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UPB1008K-E1 Datasheet PDF : 25 Pages
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PIN EXPLANATION
Pin
Pin Name
No.
Function and Application
1
GND LNA Ground pin of LNA.
2
LNAin
Input pin of low noise amplifier.
It is a single-ended open
collector design. Capacitive
coupling is required; external
matching will improve gain or
NF.
µPB1008K
Internal Equivalent Circuit
3
36
2
VCC
Regulator
6.5 k
3
VCCrf
Supply voltage pin of LNA, RF
mixer and VCO voltage
regulator.
4
GNDLO
Ground pin of 1stLO oscillator
circuit and RF Mixer.
5
1stLO-OSC1 Pin 5 & 6 are base pins of the
differential amplifier for 1stLO
oscillator. These pins requre an
LC (varacator) tank circuit to
6
1stLO-OSC2 oscilate at around 1 400 MHz.
7
VCCLO
Supply voltage pin of oscillator
circuit for 1stLO oscillator and
RF mixer.
8
PDout
This is a cirrent mode charge
pump output. For connection to
a passive RC loop filter for
driving external varactor diode
of 1stLO oscillator.
9
VCCdig
Supply voltage pin of digital
portion of the chip.
1
7
410
3
6
VCC
400
400
1.8 pF 1.8 pF
5
4.4 k
4.4 k
Regulator
idc = 941µ
4
Source
Control
Sink
Control
9
ESD
8
ESD
11
4
Data Sheet PU10282EJ01V0DS

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