UPB1009K-E1 データシートの表示（PDF） - NEC => Renesas Technology
部品番号
コンポーネント説明
メーカー
UPB1009K-E1
NEC => Renesas Technology
UPB1009K-E1 Datasheet PDF : 27 Pages
| |||
UPB1009K
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V)
Parameter
Symbol
Test Conditions
MIN. TYP. MAX. Unit
Rest current of overall IC in each Rest status without input signal, including sampling clock.
mode
MS1 = L, MS2 = L
Sleep mode Note
Is
PD1 = L, PD2 = L
1.3
2.2
3.5
mA
Warm-up mode
Iw PD1 = H, PD2 = L
10.5
13.0
15.5
mA
Calibration mode
Ic
PD1 = H, PD2 = H
18.0
22.0
25.3
mA
Active mode
Ia PD1 = L, PD2 = H
22.1
26.0
30.0
mA
Rest current of PLL block in each Current of PLL block. Overall current in calibration mode and active mode increases from that
clock mode
in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L.
Current when 1/100 divider is
used
Iw1 MS1 = L, MS2 = L
5.3
6.5
7.6
mA
Current when 256/3 divider is
used
Iw2 MS1 = L, MS2 = H
9.7
11.3
12.6
mA
Current when 1024/9 divider is
used
Iw3 MS1 = H, MS2 = L
10.2
12.1
13.5
mA
Current when 4096/65 divider is
used
Iw4 MS1 = H, MS2 = H
10.4
12.3
13.9
mA
Maximum mode control pin current
6 pin
MS1 H application
−
−
20
µA
L application
−20
−
−
µA
12 pin
MS2 H application
−
−
20
µA
L application
−20
−
−
µA
36 pin
PD1 H application
−
−
1
µA
L application
−1
−
−
µA
37 pin
PD2 H application
−
−
1
µA
L application
−1
−
−
µA
<Pre-amplifier>
fRFin = 1 575.42 MHz
Circuit Current 1
ICC1 No Signals, 1-pin current
1.9
2.3
2.7
mA
Power Gain
GLNA PRFin = −40 dBm
12.5
15.0
17.5
dB
Noise Figure
NFLNA fRFin = 1 575 MHz
−
3.0
3.5
dB
Saturated Output Power
PO(SAT)LNA PRFin = −10 dBm
−4.0
−2.7
−
dBm
Input 1dB Compression Level
PLNA−1 fRFin = 1 575.42 MHz
−25 −21.8
−
dBm
Input 3rd Order Intercept Point
IIP3LNA fRFin = 1 575.42 MHz, 1 576.42 MHz
−12
−9.5
−
dBm
Input Inpedance
Output Inpedance
ZinLNA Calculated from S-parameter where input
−
11.2 −
−
Ω
DC cut capacitance = 1 nF, output load L
j21.5
ZoutLNA = 100 n, and DC cut capacitance = 1 nF
−
16.4 −
−
Ω
j136.6
Note Most of the current flows into the ADC ladder resistor (VDDana → GNDana) in the sleep mode, and the sleep mode
current between other VCC (VDD) and GND is 10 µA maximum.
12
Share Link: