UPB1009K-E1 データシートの表示（PDF） - NEC => Renesas Technology

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UPB1009K-E1

NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT

NEC => Renesas Technology 

UPB1009K

ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V)

Parameter

<PLL Synthesizer>

Circuit Current 4

Charge Pump Output Current

Loop Filer Output (High Level)

Loop Filer Output (Low Level)

Reference Input Level

VCO Modulation Sensitivity

VCO Control Voltage

C/N

<A/D Converter>

Circuit Current 5

Resolution

Sampling Clock

Input Band Width

Integral Non-linear Error

Signal-to-noise Ratio

Signal-to-noise + Distortion Ratio

Number

Total Harmonic Distortion Ratio

Symbol

Test Conditions

ICC4 PLL, VCO current, MS1 = L, MS2 = L

Icpsink V13 pin = VCC/2

Icpsource

VOH

VOL

VREFin

KV Center frequency

VT When PLL is Locked

C/N ∆10 kHz

ICC5

ResAD

fs

ADBW

INL DC characteristics

SNR IF = 5.17 MHz, fs = 20.48 MHz

SINAD IF = 5.17 MHz, fs = 20.48 MHz

ENOB ENOB = (SINAD−1.763)/6.02

THD

IF = 5.17 MHz, fs = 20.48 MHz

Second-degree to fifth-degree distortion

components

MIN.

8.0

−0.55

0.35

VCC−0.3

−

−

−

0.5

70.0

3.1

−

−

5.1

−

22.0

20.0

3.0

−

TYP.

9.5

−0.45

0.45

−

−

0.2

100

1.3

81.0

4.1

4

−

−

0.2

25.3

25.1

3.9

−40

MAX. Unit

10.6

−0.35

0.55

−

0.2

1.6

−

2.0

−

mA

mA

mA

V

V

VPP

MHz

V

dBc/Hz

5.4

mA

−

bits

20

MHz

−

MHz

1.0

LSB

−

dB

−

dB

−

bits

−30

dBc

Remarks 1. Timing characteristics of ADC during normal operation

A buffer amplifier is internally inserted before the ADC core of the µPB1009K. The bias of this buffer amplifier

is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC.

Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in

VDDana affect the resolution of the ADC.

14

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