UPB1009K データシートの表示（PDF） - California Eastern Laboratories.

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UPB1009K

NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT

California Eastern Laboratories. 

UPB1009K

POWER-DOWN CONTROL MODE

The µPB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by

applying a voltage to the PD1 and PD2 pins), the following four modes can be used.

Mode

No.

1

2

3

4

Mode Name

Active mode

Calibration mode

Warm-up mode

Sleep mode

Test Conditions

PD1

PD2

L

H

H

H

H

L

L

L

RF Block

ON

OFF

OFF

OFF

IF Block

(IF + ADC)

ON

ON

OFF

OFF

PLL Block

ON

ON

ON

OFF

Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with

PD2.

REFERENCE CLOCK CONTROL MODE

The divided frequency can be selected as follows so that it can be shared with the TCXO of each system.

TCXO Frequency

16.368 MHz (GPS)

16.384 MHz (GPS)

19.2 MHz (W-CDMA)

14.4 MHz (PDC)

26 MHz (GSM)

Test Conditions

PD1

PD2

L

L

L

H

H

L

H

H

1/N

Phase Comparison Frequency

1/100

3/256

9/1024

65/4096

16.368 MHz

16.384 MHz

19.2 MHz

14.4 MHz

26 MHz

Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF

frequency are 61.38 MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz

and 2.556 MHz in all other cases.

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