UPD16498 データシートの表示（PDF） - NEC => Renesas Technology

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UPD16498

1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM

NEC => Renesas Technology 

µPD16498

5.8 Display Modes .................................................................................................................................................. 50

5.8.1 Partial display mode ................................................................................................................................ 50

5.8.2 Monochrome (black/white) display ........................................................................................................... 52

5.8.3 Icon display .............................................................................................................................................. 54

5.9 Reset ................................................................................................................................................................. 56

6. COMMAND REGISTERS .......................................................................................................................... 57

6.1 Control Register 1 (R0) .................................................................................................................................... 58

6.2 Control Register 2 (R1) .................................................................................................................................... 59

6.3 Reset Command (R2) ....................................................................................................................................... 60

6.4 X Address Register (R3) .................................................................................................................................. 60

6.5 Y Address Register (R4) .................................................................................................................................. 60

6.6 Duty Setting Register (R5) .............................................................................................................................. 61

6.7 AC Driver Inversion Cycle Register (R6) ........................................................................................................ 61

6.8 AC Driver Inversion Position Shift Register (R7) .......................................................................................... 62

6.9 Partial AC Driver Inversion Cycle Register (R8) ............................................................................................ 62

6.10 Partial AC Driver Inversion Position Shift Register (R9) ............................................................................ 63

6.11 Partial Display Mode Setting Register (R10) ................................................................................................ 63

6.12 Display Memory Access Register (R11)........................................................................................................ 64

6.13 Display Start Line Setting Register (R12) ..................................................................................................... 64

6.14 Blink X Address Register (R13) .................................................................................................................... 64

6.15 Blink Start Line Address Register (R14) ...................................................................................................... 65

6.16 Blink End Line Address Register (R15) ....................................................................................................... 65

6.17 Blink Data Memory Access Register (R16) .................................................................................................. 65

6.18 Inverted X Address Register (R17) ............................................................................................................... 66

6.19 Inversion Start Line Address Register (R18) ................................................................................................ 66

6.20 Inversion End Line Address Register (R19) ................................................................................................ 66

6.21 Inverted Data Memory (R20) .......................................................................................................................... 67

6.22 Partial Start Line Address Register (R21) .................................................................................................... 67

6.23 Gray Scale Data Registers 1 to 4 (R23 to R26) ............................................................................................ 68

6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) ................................................................................ 68

6.25 Power System Control Register 1 (R32) ...................................................................................................... 69

6.26 Power System Control Register 2 (R33) ...................................................................................................... 70

6.27 Power System Control Register 3 (R34) ...................................................................................................... 71

6.28 Electronic Volume Register (R35) ................................................................................................................ 72

6.29 Partial Electronic Volume Register (R36) .................................................................................................... 72

6.30 Boost Adjustment Register (R37) ................................................................................................................. 72

6.31 Static Icon Address Register (R40) ............................................................................................................. 73

6.32 Static Icon Data Register (R41) ..................................................................................................................... 73

6.33 Static Icon Contrast Register (R42) .............................................................................................................. 73

6.34 RAM Test Mode Setting Register (R44) ........................................................................................................ 74

6.35 Signature Read Register (R45) ..................................................................................................................... 74

7. LIST OF µPD16498 REGISTERS ............................................................................................................ 75

Data Sheet S15730EJ2V0DS

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